cpu.map.qmsg

微程序模拟CPU实现加减与或异或转移储存等功能。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 28 13:06:13 2008 " "Info: Processing started: Fri Nov 28 13:06:13 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cpu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CPU-rtl " "Info: Found design unit 1: CPU-rtl" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CPU " "Info: Found entity 1: CPU" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_defs.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file cpu_defs.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_defs " "Info: Found design unit 1: cpu_defs" {  } { { "cpu_defs.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu_defs.vhd" 5 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 cpu_defs-body " "Info: Found design unit 2: cpu_defs-body" {  } { { "cpu_defs.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu_defs.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cpu " "Info: Elaborating entity \"cpu\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sysbus_out cpu.vhd(191) " "Warning (10492): VHDL Process Statement warning at cpu.vhd(191): signal \"sysbus_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 191 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count cpu.vhd(193) " "Warning (10492): VHDL Process Statement warning at cpu.vhd(193): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 193 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "acc_out cpu.vhd(195) " "Warning (10492): VHDL Process Statement warning at cpu.vhd(195): signal \"acc_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 195 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "IR_out cpu.vhd(197) " "Warning (10492): VHDL Process Statement warning at cpu.vhd(197): signal \"IR_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 197 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mar_out cpu.vhd(199) " "Warning (10492): VHDL Process Statement warning at cpu.vhd(199): signal \"mar_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 199 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mdr_out cpu.vhd(201) " "Warning (10492): VHDL Process Statement warning at cpu.vhd(201): signal \"mdr_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 201 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mem cpu.vhd(203) " "Warning (10492): VHDL Process Statement warning at cpu.vhd(203): signal \"mem\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 203 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data_r_out\[5\]~reg0 data_in GND " "Warning (14130): Reduced register \"data_r_out\[5\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "data_r_out\[12\]~reg0 data_r_out\[18\]~reg0 " "Info: Duplicate register \"data_r_out\[12\]~reg0\" merged to single register \"data_r_out\[18\]~reg0\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data_r_out\[10\]~reg0 data_r_out\[16\]~reg0 " "Info: Duplicate register \"data_r_out\[10\]~reg0\" merged to single register \"data_r_out\[16\]~reg0\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "IR_out\[7\] op\[2\] " "Info: Duplicate register \"IR_out\[7\]\" merged to single register \"op\[2\]\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "IR_out\[6\] op\[1\] " "Info: Duplicate register \"IR_out\[6\]\" merged to single register \"op\[1\]\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "IR_out\[5\] op\[0\] " "Info: Duplicate register \"IR_out\[5\]\" merged to single register \"op\[0\]\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "data_r_out\[5\] GND " "Warning (13410): Pin \"data_r_out\[5\]\" stuck at GND" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "707 " "Info: Implemented 707 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "38 " "Info: Implemented 38 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "659 " "Info: Implemented 659 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "197 " "Info: Allocated 197 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 13:06:18 2008 " "Info: Processing ended: Fri Nov 28 13:06:18 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}