📄 cpu.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register add_r\[3\] register mem\[25\]\[5\] 220.07 MHz 4.544 ns Internal " "Info: Clock \"clock\" has Internal fmax of 220.07 MHz between source register \"add_r\[3\]\" and destination register \"mem\[25\]\[5\]\" (period= 4.544 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.366 ns + Longest register register " "Info: + Longest register to register delay is 4.366 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add_r\[3\] 1 REG LCFF_X22_Y15_N17 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y15_N17; Fanout = 23; REG Node = 'add_r\[3\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { add_r[3] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.621 ns) + CELL(0.228 ns) 0.849 ns Mux7~41 2 COMB LCCOMB_X21_Y15_N18 3 " "Info: 2: + IC(0.621 ns) + CELL(0.228 ns) = 0.849 ns; Loc. = LCCOMB_X21_Y15_N18; Fanout = 3; COMB Node = 'Mux7~41'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.849 ns" { add_r[3] Mux7~41 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.264 ns) + CELL(0.346 ns) 1.459 ns Decoder0~480 3 COMB LCCOMB_X21_Y15_N4 32 " "Info: 3: + IC(0.264 ns) + CELL(0.346 ns) = 1.459 ns; Loc. = LCCOMB_X21_Y15_N4; Fanout = 32; COMB Node = 'Decoder0~480'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.610 ns" { Mux7~41 Decoder0~480 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 164 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.272 ns) 2.743 ns Decoder0~493 4 COMB LCCOMB_X19_Y13_N10 8 " "Info: 4: + IC(1.012 ns) + CELL(0.272 ns) = 2.743 ns; Loc. = LCCOMB_X19_Y13_N10; Fanout = 8; COMB Node = 'Decoder0~493'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { Decoder0~480 Decoder0~493 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 164 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.877 ns) + CELL(0.746 ns) 4.366 ns mem\[25\]\[5\] 5 REG LCFF_X22_Y12_N25 2 " "Info: 5: + IC(0.877 ns) + CELL(0.746 ns) = 4.366 ns; Loc. = LCFF_X22_Y12_N25; Fanout = 2; REG Node = 'mem\[25\]\[5\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { Decoder0~493 mem[25][5] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.592 ns ( 36.46 % ) " "Info: Total cell delay = 1.592 ns ( 36.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.774 ns ( 63.54 % ) " "Info: Total interconnect delay = 2.774 ns ( 63.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.366 ns" { add_r[3] Mux7~41 Decoder0~480 Decoder0~493 mem[25][5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.366 ns" { add_r[3] {} Mux7~41 {} Decoder0~480 {} Decoder0~493 {} mem[25][5] {} } { 0.000ns 0.621ns 0.264ns 1.012ns 0.877ns } { 0.000ns 0.228ns 0.346ns 0.272ns 0.746ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns - Smallest " "Info: - Smallest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.484 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 369 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 369; COMB Node = 'clock~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns mem\[25\]\[5\] 3 REG LCFF_X22_Y12_N25 2 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X22_Y12_N25; Fanout = 2; REG Node = 'mem\[25\]\[5\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clock~clkctrl mem[25][5] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl mem[25][5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} mem[25][5] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.478 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.478 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 369 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 369; COMB Node = 'clock~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.663 ns) + CELL(0.618 ns) 2.478 ns add_r\[3\] 3 REG LCFF_X22_Y15_N17 23 " "Info: 3: + IC(0.663 ns) + CELL(0.618 ns) = 2.478 ns; Loc. = LCFF_X22_Y15_N17; Fanout = 23; REG Node = 'add_r\[3\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.281 ns" { clock~clkctrl add_r[3] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.40 % ) " "Info: Total cell delay = 1.472 ns ( 59.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.006 ns ( 40.60 % ) " "Info: Total interconnect delay = 1.006 ns ( 40.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.478 ns" { clock clock~clkctrl add_r[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.478 ns" { clock {} clock~combout {} clock~clkctrl {} add_r[3] {} } { 0.000ns 0.000ns 0.343ns 0.663ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl mem[25][5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} mem[25][5] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.478 ns" { clock clock~clkctrl add_r[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.478 ns" { clock {} clock~combout {} clock~clkctrl {} add_r[3] {} } { 0.000ns 0.000ns 0.343ns 0.663ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.366 ns" { add_r[3] Mux7~41 Decoder0~480 Decoder0~493 mem[25][5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.366 ns" { add_r[3] {} Mux7~41 {} Decoder0~480 {} Decoder0~493 {} mem[25][5] {} } { 0.000ns 0.621ns 0.264ns 1.012ns 0.877ns } { 0.000ns 0.228ns 0.346ns 0.272ns 0.746ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl mem[25][5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} mem[25][5] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.478 ns" { clock clock~clkctrl add_r[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.478 ns" { clock {} clock~combout {} clock~clkctrl {} add_r[3] {} } { 0.000ns 0.000ns 0.343ns 0.663ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "data_r_out\[6\]~reg0 reset clock 3.767 ns register " "Info: tsu for register \"data_r_out\[6\]~reg0\" (data pin = \"reset\", clock pin = \"clock\") is 3.767 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.155 ns + Longest pin register " "Info: + Longest pin to register delay is 6.155 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns reset 1 PIN PIN_M21 57 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 57; PIN Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.545 ns) + CELL(0.746 ns) 6.155 ns data_r_out\[6\]~reg0 2 REG LCFF_X22_Y15_N29 1 " "Info: 2: + IC(4.545 ns) + CELL(0.746 ns) = 6.155 ns; Loc. = LCFF_X22_Y15_N29; Fanout = 1; REG Node = 'data_r_out\[6\]~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.291 ns" { reset data_r_out[6]~reg0 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.610 ns ( 26.16 % ) " "Info: Total cell delay = 1.610 ns ( 26.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.545 ns ( 73.84 % ) " "Info: Total interconnect delay = 4.545 ns ( 73.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.155 ns" { reset data_r_out[6]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.155 ns" { reset {} reset~combout {} data_r_out[6]~reg0 {} } { 0.000ns 0.000ns 4.545ns } { 0.000ns 0.864ns 0.746ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.478 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.478 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 369 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 369; COMB Node = 'clock~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.663 ns) + CELL(0.618 ns) 2.478 ns data_r_out\[6\]~reg0 3 REG LCFF_X22_Y15_N29 1 " "Info: 3: + IC(0.663 ns) + CELL(0.618 ns) = 2.478 ns; Loc. = LCFF_X22_Y15_N29; Fanout = 1; REG Node = 'data_r_out\[6\]~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.281 ns" { clock~clkctrl data_r_out[6]~reg0 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.40 % ) " "Info: Total cell delay = 1.472 ns ( 59.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.006 ns ( 40.60 % ) " "Info: Total interconnect delay = 1.006 ns ( 40.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.478 ns" { clock clock~clkctrl data_r_out[6]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.478 ns" { clock {} clock~combout {} clock~clkctrl {} data_r_out[6]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.663ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.155 ns" { reset data_r_out[6]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.155 ns" { reset {} reset~combout {} data_r_out[6]~reg0 {} } { 0.000ns 0.000ns 4.545ns } { 0.000ns 0.864ns 0.746ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.478 ns" { clock clock~clkctrl data_r_out[6]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.478 ns" { clock {} clock~combout {} clock~clkctrl {} data_r_out[6]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.663ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock output\[7\] mem\[21\]\[7\] 11.112 ns register " "Info: tco from clock \"clock\" to destination pin \"output\[7\]\" through register \"mem\[21\]\[7\]\" is 11.112 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.468 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 369 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 369; COMB Node = 'clock~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.618 ns) 2.468 ns mem\[21\]\[7\] 3 REG LCFF_X19_Y12_N31 2 " "Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X19_Y12_N31; Fanout = 2; REG Node = 'mem\[21\]\[7\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clock~clkctrl mem[21][7] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.64 % ) " "Info: Total cell delay = 1.472 ns ( 59.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 40.36 % ) " "Info: Total interconnect delay = 0.996 ns ( 40.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clock clock~clkctrl mem[21][7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clock {} clock~combout {} clock~clkctrl {} mem[21][7] {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.550 ns + Longest register pin " "Info: + Longest register to pin delay is 8.550 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mem\[21\]\[7\] 1 REG LCFF_X19_Y12_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y12_N31; Fanout = 2; REG Node = 'mem\[21\]\[7\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem[21][7] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.309 ns) + CELL(0.357 ns) 1.666 ns Mux28~422 2 COMB LCCOMB_X19_Y17_N26 1 " "Info: 2: + IC(1.309 ns) + CELL(0.357 ns) = 1.666 ns; Loc. = LCCOMB_X19_Y17_N26; Fanout = 1; COMB Node = 'Mux28~422'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.666 ns" { mem[21][7] Mux28~422 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.053 ns) 2.930 ns Mux28~426 3 COMB LCCOMB_X18_Y11_N18 1 " "Info: 3: + IC(1.211 ns) + CELL(0.053 ns) = 2.930 ns; Loc. = LCCOMB_X18_Y11_N18; Fanout = 1; COMB Node = 'Mux28~426'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { Mux28~422 Mux28~426 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.228 ns) 4.032 ns Mux28~427 4 COMB LCCOMB_X22_Y13_N2 1 " "Info: 4: + IC(0.874 ns) + CELL(0.228 ns) = 4.032 ns; Loc. = LCCOMB_X22_Y13_N2; Fanout = 1; COMB Node = 'Mux28~427'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.102 ns" { Mux28~426 Mux28~427 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.378 ns) 4.679 ns Mux28~434 5 COMB LCCOMB_X22_Y13_N20 1 " "Info: 5: + IC(0.269 ns) + CELL(0.378 ns) = 4.679 ns; Loc. = LCCOMB_X22_Y13_N20; Fanout = 1; COMB Node = 'Mux28~434'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.647 ns" { Mux28~427 Mux28~434 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.899 ns) + CELL(1.972 ns) 8.550 ns output\[7\] 6 PIN PIN_B15 0 " "Info: 6: + IC(1.899 ns) + CELL(1.972 ns) = 8.550 ns; Loc. = PIN_B15; Fanout = 0; PIN Node = 'output\[7\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.871 ns" { Mux28~434 output[7] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.988 ns ( 34.95 % ) " "Info: Total cell delay = 2.988 ns ( 34.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.562 ns ( 65.05 % ) " "Info: Total interconnect delay = 5.562 ns ( 65.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.550 ns" { mem[21][7] Mux28~422 Mux28~426 Mux28~427 Mux28~434 output[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.550 ns" { mem[21][7] {} Mux28~422 {} Mux28~426 {} Mux28~427 {} Mux28~434 {} output[7] {} } { 0.000ns 1.309ns 1.211ns 0.874ns 0.269ns 1.899ns } { 0.000ns 0.357ns 0.053ns 0.228ns 0.378ns 1.972ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clock clock~clkctrl mem[21][7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clock {} clock~combout {} clock~clkctrl {} mem[21][7] {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.550 ns" { mem[21][7] Mux28~422 Mux28~426 Mux28~427 Mux28~434 output[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.550 ns" { mem[21][7] {} Mux28~422 {} Mux28~426 {} Mux28~427 {} Mux28~434 {} output[7] {} } { 0.000ns 1.309ns 1.211ns 0.874ns 0.269ns 1.899ns } { 0.000ns 0.357ns 0.053ns 0.228ns 0.378ns 1.972ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "mem_addr\[1\] output\[5\] 13.389 ns Longest " "Info: Longest tpd from source pin \"mem_addr\[1\]\" to destination pin \"output\[5\]\" is 13.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns mem_addr\[1\] 1 PIN PIN_H11 40 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H11; Fanout = 40; PIN Node = 'mem_addr\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem_addr[1] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.158 ns) + CELL(0.272 ns) 6.237 ns Mux30~246 2 COMB LCCOMB_X22_Y12_N10 1 " "Info: 2: + IC(5.158 ns) + CELL(0.272 ns) = 6.237 ns; Loc. = LCCOMB_X22_Y12_N10; Fanout = 1; COMB Node = 'Mux30~246'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.430 ns" { mem_addr[1] Mux30~246 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.068 ns) + CELL(0.357 ns) 7.662 ns Mux30~249 3 COMB LCCOMB_X14_Y14_N4 1 " "Info: 3: + IC(1.068 ns) + CELL(0.357 ns) = 7.662 ns; Loc. = LCCOMB_X14_Y14_N4; Fanout = 1; COMB Node = 'Mux30~249'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.425 ns" { Mux30~246 Mux30~249 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.346 ns) 9.088 ns Mux30~250 4 COMB LCCOMB_X21_Y16_N6 1 " "Info: 4: + IC(1.080 ns) + CELL(0.346 ns) = 9.088 ns; Loc. = LCCOMB_X21_Y16_N6; Fanout = 1; COMB Node = 'Mux30~250'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.426 ns" { Mux30~249 Mux30~250 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.357 ns) 10.008 ns Mux30~257 5 COMB LCCOMB_X21_Y16_N16 1 " "Info: 5: + IC(0.563 ns) + CELL(0.357 ns) = 10.008 ns; Loc. = LCCOMB_X21_Y16_N16; Fanout = 1; COMB Node = 'Mux30~257'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.920 ns" { Mux30~250 Mux30~257 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.449 ns) + CELL(1.932 ns) 13.389 ns output\[5\] 6 PIN PIN_G12 0 " "Info: 6: + IC(1.449 ns) + CELL(1.932 ns) = 13.389 ns; Loc. = PIN_G12; Fanout = 0; PIN Node = 'output\[5\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.381 ns" { Mux30~257 output[5] } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.071 ns ( 30.41 % ) " "Info: Total cell delay = 4.071 ns ( 30.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.318 ns ( 69.59 % ) " "Info: Total interconnect delay = 9.318 ns ( 69.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.389 ns" { mem_addr[1] Mux30~246 Mux30~249 Mux30~250 Mux30~257 output[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.389 ns" { mem_addr[1] {} mem_addr[1]~combout {} Mux30~246 {} Mux30~249 {} Mux30~250 {} Mux30~257 {} output[5] {} } { 0.000ns 0.000ns 5.158ns 1.068ns 1.080ns 0.563ns 1.449ns } { 0.000ns 0.807ns 0.272ns 0.357ns 0.346ns 0.357ns 1.932ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
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