📄 cpu.map.rpt
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; -- 4 input functions ; 24 ;
; -- <=3 input functions ; 62 ;
; ; ;
; Combinational ALUTs by mode ; ;
; -- normal mode ; 323 ;
; -- extended LUT mode ; 3 ;
; -- arithmetic mode ; 13 ;
; -- shared arithmetic mode ; 0 ;
; ; ;
; Estimated ALUT/register pairs used ; 504 ;
; ; ;
; Total registers ; 360 ;
; -- Dedicated logic registers ; 360 ;
; -- I/O registers ; 0 ;
; ; ;
; Estimated ALMs: partially or completely used ; 252 ;
; ; ;
; I/O pins ; 48 ;
; Maximum fan-out node ; clock ;
; Maximum fan-out ; 360 ;
; Total fan-out ; 3113 ;
; Average fan-out ; 4.17 ;
+-----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |CPU ; 339 (339) ; 360 (360) ; 0 ; 0 ; 0 ; 0 ; 0 ; 48 ; 0 ; |CPU ; work ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; data_r_out[5]~reg0 ; Stuck at GND due to stuck port data_in ;
; data_r_out[12]~reg0 ; Merged with data_r_out[18]~reg0 ;
; data_r_out[10]~reg0 ; Merged with data_r_out[16]~reg0 ;
; IR_out[7] ; Merged with op[2] ;
; IR_out[6] ; Merged with op[1] ;
; IR_out[5] ; Merged with op[0] ;
; Total Number of Removed Registers = 6 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 360 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 5 ;
; Number of registers using Asynchronous Clear ; 304 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 315 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; mem[1][0] ; 2 ;
; mem[5][0] ; 2 ;
; mem[4][0] ; 2 ;
; mem[6][0] ; 2 ;
; mem[1][1] ; 2 ;
; mem[3][1] ; 2 ;
; mem[7][1] ; 2 ;
; mem[0][1] ; 2 ;
; mem[4][1] ; 2 ;
; mem[1][2] ; 2 ;
; mem[3][2] ; 2 ;
; mem[0][2] ; 2 ;
; mem[4][2] ; 2 ;
; mem[5][3] ; 2 ;
; mem[2][3] ; 2 ;
; mem[2][5] ; 2 ;
; mem[3][5] ; 2 ;
; mem[4][6] ; 2 ;
; mem[1][6] ; 2 ;
; mem[4][7] ; 2 ;
; mem[5][7] ; 2 ;
; mem[3][7] ; 2 ;
; Total number of inverted registers = 22 ; ;
+-----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1 ; 3 bits ; 9 ALUTs ; 6 ALUTs ; 3 ALUTs ; Yes ; |CPU|sysbus[5] ;
; 3:1 ; 2 bits ; 4 ALUTs ; 4 ALUTs ; 0 ALUTs ; No ; |CPU|add_r~8 ;
; 4:1 ; 5 bits ; 10 ALUTs ; 10 ALUTs ; 0 ALUTs ; No ; |CPU|sysbus~20 ;
; 4:1 ; 8 bits ; 16 ALUTs ; 16 ALUTs ; 0 ALUTs ; No ; |CPU|acc~36 ;
; 38:1 ; 3 bits ; 75 ALUTs ; 75 ALUTs ; 0 ALUTs ; No ; |CPU|Mux28 ;
; 38:1 ; 5 bits ; 125 ALUTs ; 125 ALUTs ; 0 ALUTs ; No ; |CPU|Mux35 ;
; 36:1 ; 8 bits ; 192 ALUTs ; 176 ALUTs ; 16 ALUTs ; No ; |CPU|mdr~27 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Fri Nov 28 13:06:13 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu
Info: Found 2 design units, including 1 entities, in source file cpu.vhd
Info: Found design unit 1: CPU-rtl
Info: Found entity 1: CPU
Info: Found 2 design units, including 0 entities, in source file cpu_defs.vhd
Info: Found design unit 1: cpu_defs
Info: Found design unit 2: cpu_defs-body
Info: Elaborating entity "cpu" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at cpu.vhd(191): signal "sysbus_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cpu.vhd(193): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cpu.vhd(195): signal "acc_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cpu.vhd(197): signal "IR_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cpu.vhd(199): signal "mar_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cpu.vhd(201): signal "mdr_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cpu.vhd(203): signal "mem" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (14130): Reduced register "data_r_out[5]~reg0" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "data_r_out[12]~reg0" merged to single register "data_r_out[18]~reg0"
Info: Duplicate register "data_r_out[10]~reg0" merged to single register "data_r_out[16]~reg0"
Info: Duplicate register "IR_out[7]" merged to single register "op[2]"
Info: Duplicate register "IR_out[6]" merged to single register "op[1]"
Info: Duplicate register "IR_out[5]" merged to single register "op[0]"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "data_r_out[5]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 707 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 38 output pins
Info: Implemented 659 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
Info: Allocated 197 megabytes of memory during processing
Info: Processing ended: Fri Nov 28 13:06:18 2008
Info: Elapsed time: 00:00:05
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