macros.v

appnote65_quickmips_ahb_interface_design_example AHB接口设计

endmodule // inv_gclkbuff_25um

`endif


`ifdef tripados_25um
`else
`define tripados_25um
module tripados_25um( EN , P );
input EN;
output P;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(EN), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(VCC), .OSEL(VCC) );

endmodule // tripados_25um

`endif

`ifdef tripadod_25um
`else
`define tripadod_25um
module tripadod_25um( EN , P );
input EN;
output P;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I3 ( .EQE(VCC), .ESEL(VCC), .IE(EN), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(GND), .OSEL(VCC) );

endmodule // tripadod_25um

`endif

`ifdef tripadff_25um
`else
`define tripadff_25um
module tripadff_25um( A , EN, FFCLK, FFCLR, P, Q );
input A, EN;
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
output P, Q;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(EN), .IP(P), .IQC(FFCLK), .IQE(GND),
           .IQR(FFCLR), .IZ(Q), .OQI(A), .OSEL(GND) );

endmodule // tripadff_25um

`endif

`ifdef tripad_25um
`else
`define tripad_25um
module tripad_25um( A , EN, P );
input A, EN;
output P;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(EN), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // tripad_25um

`endif

`ifdef outpadff_25um
`else
`define outpadff_25um
module outpadff_25um( A , FFCLK, FFCLR, P, P_FB );
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input A;
output P, P_FB;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(FFCLK), .IQE(GND),
           .IQR(FFCLR), .OQI(A), .OQQ(P_FB), .OSEL(GND) );

endmodule // outpadff_25um

`endif

`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // outpad_25um

`endif

`ifdef inpadff_25um
`else
`define inpadff_25um
module inpadff_25um( FFCLK , FFCLR, FFEN, P, FFQ, Q );
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input FFEN;
output FFQ;
input P;
output Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(FFCLK), .IQE(FFEN),
           .IQQ(FFQ), .IQR(FFCLR), .IZ(Q), .OQI(gnd), .OSEL(vcc) );

endmodule // inpadff_25um

`endif

`ifdef io_buff_25um
`else
`define io_buff_25um
module io_buff_25um( I , O );
input I;
output O;
parameter ql_gate = `IOCONTROL;
supply0 gnd;
supply1 vcc;

inbuffcell_25um I1 ( .I(I), .IP(gnd), .IS(vcc), .O(O) );

endmodule // io_buff_25um

`endif

`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // inpad_25um

`endif

`ifdef hdpad_25um
`else
`define hdpad_25um
module hdpad_25um( IP , O );
input IP;
output O;
parameter ql_gate = `IOCONTROL;
supply0 gnd;

iocontrol I1 ( .IP(IP), .IS(GND), .O(O) );

endmodule // hdpad_25um

`endif

`ifdef eio_25um
`else
`define eio_25um
module eio_25um( A2 , EN, FFCLK, FFCLR, I_EN, OE_EN, OESEL, OSEL, FFQ, P_FB, Q,
                 P );
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input A2, EN;
output FFQ;
input I_EN, OE_EN, OESEL, OSEL;
inout P;
output P_FB, Q;
parameter ql_gate = `BIDIR;

eio_cell I1 ( .EQE(OE_EN), .ESEL(OESEL), .IE(EN), .IP(P), .IQC(FFCLK), .IQE(I_EN),
           .IQQ(FFQ), .IQR(FFCLR), .IZ(Q), .OQI(A2), .OQQ(P_FB), .OSEL(OSEL) );

endmodule // eio_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P /*synthesis syn_isclock=1 */;
output Q;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef bipados_25um
`else
`define bipados_25um
module bipados_25um( EN , Q, P );
input EN;
inout P;
output Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(EN), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // bipados_25um

`endif

`ifdef bipadoff_25um
`else
`define bipadoff_25um
module bipadoff_25um( A2 , EN, FFCLK, FFCLR, P_FB, Q, P );
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input A2, EN;
inout P;
output P_FB, Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(EN), .IP(P), .IQC(FFCLK), .IQE(gnd),
           .IQR(FFCLR), .IZ(Q), .OQI(A2), .OQQ(P_FB), .OSEL(gnd) );

endmodule // bipadoff_25um

`endif

`ifdef bipadod_25um
`else
`define bipadod_25um
module bipadod_25um( EN , Q, P );
input EN;
inout P;
output Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(EN), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(gnd), .OSEL(vcc) );

endmodule // bipadod_25um

`endif

`ifdef bipadioff_25um
`else
`define bipadioff_25um
module bipadioff_25um( A2 , EN, FFCLK, FFCLR, inFFEN, FFQ, P_FB, Q, P );
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input A2, EN;
output FFQ;
input inFFEN;
inout P;
output P_FB, Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(EN), .IP(P), .IQC(FFCLK), .IQE(inFFEN),
           .IQQ(FFQ), .IQR(FFCLR), .IZ(Q), .OQI(A2), .OQQ(P_FB), .OSEL(gnd) );

endmodule // bipadioff_25um

`endif

`ifdef bipadiff_25um
`else
`define bipadiff_25um
module bipadiff_25um( A2 , EN, FFCLK, FFCLR, FFEN, FFQ, Q, P );
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input FFEN;
input A2, EN;
output FFQ;
inout P;
output Q;
parameter ql_gate = `BIDIR;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(EN), .IP(P), .IQC(FFCLK), .IQE(FFEN),
           .IQQ(FFQ), .IQR(FFCLR), .IZ(Q), .OQI(A2), .OSEL(vcc) );

endmodule // bipadiff_25um

`endif

`ifdef bipadeioff_25um
`else
`define bipadeioff_25um
module bipadeioff_25um( A2 , EN, FFCLK, FFCLR, I_EN, OE_EN, FFQ, P_FB, Q, P );
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input A2, EN;
output FFQ;
input I_EN, OE_EN;
inout P;
output P_FB, Q;
parameter ql_gate = `BIDIR;
supply0 gnd;

eio_cell I1 ( .EQE(OE_EN), .ESEL(gnd), .IE(EN), .IP(P), .IQC(FFCLK), .IQE(I_EN),
           .IQQ(FFQ), .IQR(FFCLR), .IZ(Q), .OQI(A2), .OQQ(P_FB), .OSEL(gnd) );

endmodule // bipadeioff_25um

`endif

`ifdef bipad_25um
`else
`define bipad_25um
module bipad_25um( A , EN, Q, P );
input A, EN;
inout P;
output Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I2 ( .EQE(vcc), .ESEL(vcc), .IE(EN), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(A), .OSEL(vcc) );

endmodule // bipad_25um

`endif

`ifdef ckpadp5
`else
`define ckpadp5
module ckpadp5( P , Q );
input P /*synthesis syn_isclock=1 */;
output Q;
parameter ql_gate = `CLOCKB;

ckcell5 I3 ( .IC(Q), .IP(P) );

endmodule // ckpadp5

`endif

`ifdef ucebitb0
`else
`define ucebitb0
module ucebitb0( CLK , CLR, ENH1, ENH2, ENH3, ENH4, ENL1, ENL2, ENL3, QFB, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input ENH1, ENH2, ENH3, ENH4, ENL1, ENL2, ENL3;
output Q;
input QFB;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

lcell2 I_1 ( .A1(ENH2), .A2(ENL3), .A3(ENH3), .A4(ENL2), .A5(ENH4), .A6(ENL1),
          .B1(GND), .B2(GND), .C1(VCC), .C2(QFB), .D1(QFB), .D2(GND), .E1(GND),
          .E2(GND), .F1(VCC), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND),
          .MP(GND), .MS(VCC), .NP(GND), .NS(GND), .OP(ENH1), .OS(GND), .QC(CLK),
          .QR(CLR), .QS(GND), .QZ(Q) );

endmodule // ucebitb0

`endif

`ifdef udrn6_p2
`else
`define udrn6_p2
module udrn6_p2( ARST , CLK, D, D0, D1, D2N, DOWN, LDN, Q, U0, U1, U2N, UPN,
                 ALLONEN, ALLZERO );
output ALLONEN, ALLZERO;
input CLK /* synthesis syn_isclock=1 */;
input ARST;
 input [5:0] D;
input D0, D1, D2N, DOWN, LDN;
 input [5:0] Q;
input U0, U1, U2N, UPN;
wire N_15;
wire N_16;
wire N_12;
wire N_14;
wire N_9;
wire N_10;
wire N_7;
supply1 VCC;
supply0 GND;

or2i0 I_12 ( .A(ALLONEN), .B(N_16), .Q(N_15) );
and5i3 I_10 ( .A(U0), .B(U1), .C(DOWN), .D(U2N), .E(UPN), .Q(N_12) );
and5i2 I_11 ( .A(DOWN), .B(UPN), .C(D2N), .D(D1), .E(D0), .Q(N_16) );
and16i7 I_5 ( .A(VCC), .B(VCC), .C(VCC), .D(VCC), .E(VCC), .F(VCC), .G(D2N), .H(UPN),
           .I(DOWN), .J(D1), .K(D0), .L(Q[1]), .M(Q[2]), .N(Q[3]