macros.v

appnote65_quickmips_ahb_interface_design_example AHB接口设计

bipad_25um I11 ( .A(A[6]), .EN(EN), .P(P[6]), .Q(Q[6]) );
bipad_25um I12 ( .A(A[7]), .EN(EN), .P(P[7]), .Q(Q[7]) );
bipad_25um I13 ( .A(A[3]), .EN(EN), .P(P[3]), .Q(Q[3]) );
bipad_25um I14 ( .A(A[2]), .EN(EN), .P(P[2]), .Q(Q[2]) );
bipad_25um I15 ( .A(A[1]), .EN(EN), .P(P[1]), .Q(Q[1]) );
bipad_25um I16 ( .A(A[0]), .EN(EN), .P(P[0]), .Q(Q[0]) );

endmodule // bpad16_25um

`endif

`ifdef rgec8_25um
`else
`define rgec8_25um
module rgec8_25um( CLK , CLR, D, EN, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
 input [7:0] D;
input EN;
 output [7:0] Q;
supply0 gnd;

dffepc_2 I6 ( .CLK(CLK), .CLR(CLR), .D1(D[6]), .D2(D[7]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[6]), .Q2(Q[7]) );
dffepc_2 I7 ( .CLK(CLK), .CLR(CLR), .D1(D[4]), .D2(D[5]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[4]), .Q2(Q[5]) );
dffepc_2 I8 ( .CLK(CLK), .CLR(CLR), .D1(D[2]), .D2(D[3]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[2]), .Q2(Q[3]) );
dffepc_2 I9 ( .CLK(CLK), .CLR(CLR), .D1(D[0]), .D2(D[1]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rgec8_25um

`endif

`ifdef rgec4_25um
`else
`define rgec4_25um
module rgec4_25um( CLK , CLR, D, EN, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
 input [3:0] D;
input EN;
 output [3:0] Q;
supply0 gnd;

dffepc_2 I8 ( .CLK(CLK), .CLR(CLR), .D1(D[2]), .D2(D[3]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[2]), .Q2(Q[3]) );
dffepc_2 I9 ( .CLK(CLK), .CLR(CLR), .D1(D[0]), .D2(D[1]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rgec4_25um

`endif

`ifdef rgec16_25um
`else
`define rgec16_25um
module rgec16_25um( CLK , CLR, D, EN, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
 input [15:0] D;
input EN;
 output [15:0] Q;
supply0 gnd;

dffepc_2 I2 ( .CLK(CLK), .CLR(CLR), .D1(D[14]), .D2(D[15]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[14]), .Q2(Q[15]) );
dffepc_2 I3 ( .CLK(CLK), .CLR(CLR), .D1(D[12]), .D2(D[13]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[12]), .Q2(Q[13]) );
dffepc_2 I4 ( .CLK(CLK), .CLR(CLR), .D1(D[10]), .D2(D[11]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[10]), .Q2(Q[11]) );
dffepc_2 I5 ( .CLK(CLK), .CLR(CLR), .D1(D[8]), .D2(D[9]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[8]), .Q2(Q[9]) );
dffepc_2 I6 ( .CLK(CLK), .CLR(CLR), .D1(D[6]), .D2(D[7]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[6]), .Q2(Q[7]) );
dffepc_2 I7 ( .CLK(CLK), .CLR(CLR), .D1(D[4]), .D2(D[5]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[4]), .Q2(Q[5]) );
dffepc_2 I8 ( .CLK(CLK), .CLR(CLR), .D1(D[2]), .D2(D[3]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[2]), .Q2(Q[3]) );
dffepc_2 I9 ( .CLK(CLK), .CLR(CLR), .D1(D[0]), .D2(D[1]), .EN1(EN), .EN2(EN),
           .PRE(gnd), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rgec16_25um

`endif

`ifdef rge8_25um
`else
`define rge8_25um
module rge8_25um( CLK , D, EN, Q );
input CLK /* synthesis syn_isclock=1 */;
 input [7:0] D;
input EN;
 output [7:0] Q;

dffe_2 I6 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .EN1(EN), .EN2(EN), .Q1(Q[6]),
         .Q2(Q[7]) );
dffe_2 I7 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .EN1(EN), .EN2(EN), .Q1(Q[4]),
         .Q2(Q[5]) );
dffe_2 I8 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .EN1(EN), .EN2(EN), .Q1(Q[2]),
         .Q2(Q[3]) );
dffe_2 I9 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .EN1(EN), .EN2(EN), .Q1(Q[0]),
         .Q2(Q[1]) );

endmodule // rge8_25um

`endif

`ifdef rge4_25um
`else
`define rge4_25um
module rge4_25um( CLK , D, EN, Q );
input CLK /* synthesis syn_isclock=1 */;
 input [3:0] D;
input EN;
 output [3:0] Q;

dffe_2 I8 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .EN1(EN), .EN2(EN), .Q1(Q[2]),
         .Q2(Q[3]) );
dffe_2 I9 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .EN1(EN), .EN2(EN), .Q1(Q[0]),
         .Q2(Q[1]) );

endmodule // rge4_25um

`endif

`ifdef rge16_25um
`else
`define rge16_25um
module rge16_25um( CLK , D, EN, Q );
input CLK /* synthesis syn_isclock=1 */;
 input [15:0] D;
input EN;
 output [15:0] Q;

dffe_2 I2 ( .CLK(CLK), .D1(D[14]), .D2(D[15]), .EN1(EN), .EN2(EN), .Q1(Q[14]),
         .Q2(Q[15]) );
dffe_2 I3 ( .CLK(CLK), .D1(D[12]), .D2(D[13]), .EN1(EN), .EN2(EN), .Q1(Q[12]),
         .Q2(Q[13]) );
dffe_2 I4 ( .CLK(CLK), .D1(D[10]), .D2(D[11]), .EN1(EN), .EN2(EN), .Q1(Q[10]),
         .Q2(Q[11]) );
dffe_2 I5 ( .CLK(CLK), .D1(D[8]), .D2(D[9]), .EN1(EN), .EN2(EN), .Q1(Q[8]),
         .Q2(Q[9]) );
dffe_2 I6 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .EN1(EN), .EN2(EN), .Q1(Q[6]),
         .Q2(Q[7]) );
dffe_2 I7 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .EN1(EN), .EN2(EN), .Q1(Q[4]),
         .Q2(Q[5]) );
dffe_2 I8 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .EN1(EN), .EN2(EN), .Q1(Q[2]),
         .Q2(Q[3]) );
dffe_2 I9 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .EN1(EN), .EN2(EN), .Q1(Q[0]),
         .Q2(Q[1]) );

endmodule // rge16_25um

`endif

`ifdef rgc8_25um
`else
`define rgc8_25um
module rgc8_25um( CLK , CLR, D, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
 input [7:0] D;
 output [7:0] Q;

dffc_2 I6 ( .CLK(CLK), .CLR(CLR), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dffc_2 I7 ( .CLK(CLK), .CLR(CLR), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dffc_2 I8 ( .CLK(CLK), .CLR(CLR), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );
dffc_2 I9 ( .CLK(CLK), .CLR(CLR), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );

endmodule // rgc8_25um

`endif

`ifdef rgc4_25um
`else
`define rgc4_25um
module rgc4_25um( CLK , CLR, D, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
 input [3:0] D;
 output [3:0] Q;

dffc_2 I8 ( .CLK(CLK), .CLR(CLR), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );
dffc_2 I9 ( .CLK(CLK), .CLR(CLR), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );

endmodule // rgc4_25um

`endif

`ifdef rgc16_25um
`else
`define rgc16_25um
module rgc16_25um( CLK , CLR, D, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
 input [15:0] D;
 output [15:0] Q;

dffc_2 I2 ( .CLK(CLK), .CLR(CLR), .D1(D[14]), .D2(D[15]), .Q1(Q[14]), .Q2(Q[15]) );
dffc_2 I3 ( .CLK(CLK), .CLR(CLR), .D1(D[12]), .D2(D[13]), .Q1(Q[12]), .Q2(Q[13]) );
dffc_2 I4 ( .CLK(CLK), .CLR(CLR), .D1(D[10]), .D2(D[11]), .Q1(Q[10]), .Q2(Q[11]) );
dffc_2 I5 ( .CLK(CLK), .CLR(CLR), .D1(D[8]), .D2(D[9]), .Q1(Q[8]), .Q2(Q[9]) );
dffc_2 I6 ( .CLK(CLK), .CLR(CLR), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dffc_2 I7 ( .CLK(CLK), .CLR(CLR), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dffc_2 I8 ( .CLK(CLK), .CLR(CLR), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );
dffc_2 I9 ( .CLK(CLK), .CLR(CLR), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );

endmodule // rgc16_25um

`endif

`ifdef rg8_25um
`else
`define rg8_25um
module rg8_25um( CLK , D, Q );
input CLK /* synthesis syn_isclock=1 */;
 input [7:0] D;
 output [7:0] Q;

dff_2 I3 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I4 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );
dff_2 I6 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );

endmodule // rg8_25um

`endif

`ifdef rg4_25um
`else
`define rg4_25um
module rg4_25um( CLK , D, Q );
input CLK /* synthesis syn_isclock=1 */;
 input [3:0] D;
 output [3:0] Q;

dff_2 I3 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I4 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rg4_25um

`endif

`ifdef rg16_25um
`else
`define rg16_25um
module rg16_25um( CLK , D, Q );
input CLK /* synthesis syn_isclock=1 */;
 input [15:0] D;
 output [15:0] Q;

dff_2 I6 ( .CLK(CLK), .D1(D[14]), .D2(D[15]), .Q1(Q[14]), .Q2(Q[15]) );
dff_2 I7 ( .CLK(CLK), .D1(D[12]), .D2(D[13]), .Q1(Q[12]), .Q2(Q[13]) );
dff_2 I8 ( .CLK(CLK), .D1(D[10]), .D2(D[11]), .Q1(Q[10]), .Q2(Q[11]) );
dff_2 I9 ( .CLK(CLK), .D1(D[8]), .D2(D[9]), .Q1(Q[8]), .Q2(Q[9]) );
dff_2 I2 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I3 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I4 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rg16_25um

`endif

`ifdef dffepc_2
`else
`define dffepc_2
module dffepc_2( CLK , CLR, D1, D2, EN1, EN2, PRE, Q1, Q2 );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input PRE /* synthesis syn_isclock=1 */;
input D1, D2, EN1, EN2;
output Q1, Q2;
supply1 vcc;
supply0 gnd;

super_logic I4 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(Q1), .B2(gnd), .C1(D1), .C2(gnd), .D1(Q2), .D2(gnd), .E1(D2),
              .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd), .F5(vcc),
              .F6(gnd), .MP(gnd), .MS(EN1), .NP(gnd), .NS(EN2), .OP(gnd),
              .OS(gnd), .PP(gnd), .PS(gnd), .Q2Z(Q2), .QC(CLK), .QR(CLR),
              .QS(PRE), .QZ(Q1) );

endmodule // dffepc_2

`endif

`ifdef dffe_2
`else
`define dffe_2
module dffe_2( CLK , D1, D2, EN1, EN2, Q1, Q2 );
input CLK /* synthesis syn_isclock=1 */;
input D1, D2, EN1, EN2;
output Q1, Q2;
supply0 gnd;
supply1 vcc;

super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(Q1), .B2(gnd), .C1(D1), .C2(gnd), .D1(Q2), .D2(gnd), .E1(D2),
              .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd), .F5(vcc),
              .F6(gnd), .MP(gnd), .MS(EN1), .NP(gnd), .NS(EN2), .OP(gnd),
              .OS(gnd), .PP(gnd), .PS(gnd), .Q2Z(Q2), .QC(CLK), .QR(gnd),
              .QS(gnd), .QZ(Q1) );

endmodule // dffe_2

`endif

`ifdef dffc_2
`else
`define dffc_2
module dffc_2( CLK , CLR, D1, D2, Q1, Q2 );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input D1, D2;
output Q1, Q2;
supply1 vcc;
supply0 gnd;

super_logic I3 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(gnd), .MS(gnd), .NP(gnd), .NS(vcc),
              .OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
              .QR(CLR), .QS(gnd), .QZ(Q1) );

endmodule // dffc_2

`endif

`ifdef dff_2
`else
`define dff_2
module dff_2( CLK , D1, D2, Q1, Q2 );
input CLK /* synthesis syn_isclock=1 */;
input D1, D2;
output Q1, Q2;
supply1 vcc;
supply0 gnd;

super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(gnd), .MS(vcc), .NP(gnd), .NS(vcc),
              .OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
              .QR(gnd), .QS(gnd), .QZ(Q1) );

endmodule // dff_2

`endif

`ifdef super_logic
`else
`define super_logic
module super_logic( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                    F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC,
                    QR, QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC /* synthesis syn_isclock=1 */;
input QR /* synthesis syn_isclock=1 */;
input QS /* synthesis syn_isclock=1 */;
output QZ;
parameter ql_gate = `LOGIC;

super_cell I2 ( .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .AZ(AZ),
             .B1(B1), .B2(B2), .C1(C1), .C2(C2), .D1(D1), .D2(D2), .E1(E1),
             .E2(E2), .F1(F1), .F2(F2), .F3(F3), .F4(F4), .F5(F5), .F6(F6),
             .FZ(FZ), .MP(MP), .MS(MS), .NP(NP), .NS(NS), .NZ(NZ), .OP(OP),
             .OS(OS), .OZ(OZ), .PP(PP), .PS(PS), .Q2Z(Q2Z), .QC(QC), .QR(QR),
             .QS(QS), .QZ(QZ) );

endmodule // super_logic

`endif

`ifdef gclkbuff_25um
`else
`define gclkbuff_25um
module gclkbuff_25um( A , Z );
input A;
output Z;
parameter ql_gate = `HSCKMUX;
supply1 vcc;

hsckmux I1 ( .IC(A), .IS(vcc), .IZ(Z) );

endmodule // gclkbuff_25um

`endif

`ifdef inv_gclkbuff_25um
`else
`define inv_gclkbuff_25um
module inv_gclkbuff_25um( A , Z );
input A;
output Z;
supply1 vcc;
supply0 gnd;
wire N_1;

super_logic I1 ( .A1(vcc), .A2(A), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd), .AZ(N_1),
              .B1(gnd), .B2(gnd), .C1(gnd), .C2(gnd), .D1(gnd), .D2(gnd),
              .E1(gnd), .E2(gnd), .F1(gnd), .F2(gnd), .F3(gnd), .F4(gnd),
              .F5(gnd), .F6(gnd), .MP(gnd), .MS(gnd), .NP(gnd), .NS(gnd),
              .OP(gnd), .OS(gnd), .PP(gnd), .PS(gnd), .QC(gnd), .QR(gnd),
              .QS(vcc) );
gclkbuff_25um I2 ( .A(N_1), .Z(Z) );