macros.v

appnote65_quickmips_ahb_interface_design_example AHB接口设计

outpad_25um I5 ( .A(inv), .P(Vo_neg) );
outpad_25um I6 ( .A(non_inv), .P(Vo_pos) );
super_logic I4 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(gnd), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(input2diff), .MS(gnd), .NP(input2diff),
              .NS(gnd), .NZ(inv), .OP(gnd), .OS(gnd), .OZ(non_inv), .PP(vcc),
              .PS(gnd), .QC(gnd), .QR(gnd), .QS(vcc) );

endmodule // lvpecl_outpad_25dc

`endif

`ifdef lvpecl_outpad_25ac
`else
`define lvpecl_outpad_25ac
module lvpecl_outpad_25ac( input2diff , Vo_neg, Vo_pos );
input input2diff;
output Vo_neg, Vo_pos;
wire inv;
wire non_inv;
supply1 vcc;
supply0 gnd;

tripadod_25um I7 ( .EN(non_inv), .P(Vo_neg) );
tripadod_25um I8 ( .EN(inv), .P(Vo_pos) );
super_logic I9 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(gnd), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(input2diff), .MS(gnd), .NP(input2diff),
              .NS(gnd), .NZ(inv), .OP(gnd), .OS(gnd), .OZ(non_inv), .PP(vcc),
              .PS(gnd), .QC(gnd), .QR(gnd), .QS(vcc) );

endmodule // lvpecl_outpad_25ac

`endif

`ifdef lvpecl_inpad_25
`else
`define lvpecl_inpad_25
module lvpecl_inpad_25( Vin_neg , Vin_pos, diff_input );
output diff_input;
input Vin_neg, Vin_pos;
wire N_1;
wire N_2;

and2i1 I5 ( .A(N_1), .B(N_2), .Q(diff_input) );
inpad_25um I6 ( .P(Vin_neg), .Q(N_2) );
inpad_25um I7 ( .P(Vin_pos), .Q(N_1) );

endmodule // lvpecl_inpad_25

`endif

`ifdef reg_lvds_outpad_25dc
`else
`define reg_lvds_outpad_25dc
module reg_lvds_outpad_25dc( clk , clr, input2diff, Vo_neg, Vo_pos );
input clk /* synthesis syn_isclock=1 */;
input clr /* synthesis syn_isclock=1 */;
input input2diff;
output Vo_neg, Vo_pos;
wire inv;
wire non_inv;
supply1 vcc;
supply0 gnd;

super_logic I4 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(gnd), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(input2diff), .MS(gnd), .NP(input2diff),
              .NS(gnd), .NZ(inv), .OP(gnd), .OS(gnd), .OZ(non_inv), .PP(vcc),
              .PS(gnd), .QC(gnd), .QR(gnd), .QS(vcc) );
outpadff_25um I2 ( .A(non_inv), .FFCLK(clk), .FFCLR(clr), .P(Vo_pos) );
outpadff_25um I1 ( .A(inv), .FFCLK(clk), .FFCLR(clr), .P(Vo_neg) );

endmodule // reg_lvds_outpad_25dc

`endif

`ifdef lvds_outpad_25dc
`else
`define lvds_outpad_25dc
module lvds_outpad_25dc( input2diff , Vo_neg, Vo_pos );
input input2diff;
output Vo_neg, Vo_pos;
wire inv;
wire non_inv;
supply1 vcc;
supply0 gnd;

outpad_25um I5 ( .A(inv), .P(Vo_neg) );
outpad_25um I6 ( .A(non_inv), .P(Vo_pos) );
super_logic I4 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(gnd), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(input2diff), .MS(gnd), .NP(input2diff),
              .NS(gnd), .NZ(inv), .OP(gnd), .OS(gnd), .OZ(non_inv), .PP(vcc),
              .PS(gnd), .QC(gnd), .QR(gnd), .QS(vcc) );

endmodule // lvds_outpad_25dc

`endif

`ifdef lvds_inpad_25dc
`else
`define lvds_inpad_25dc
module lvds_inpad_25dc( Vin_neg , Vin_pos, diff_input );
output diff_input;
input Vin_neg, Vin_pos;
wire N_1;
wire N_2;

and2i1 I5 ( .A(N_1), .B(N_2), .Q(diff_input) );
inpad_25um I6 ( .P(Vin_neg), .Q(N_2) );
inpad_25um I7 ( .P(Vin_pos), .Q(N_1) );

endmodule // lvds_inpad_25dc

`endif

`ifdef uct8p2
`else
`define uct8p2
module uct8p2( CLK , CLR, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
 output [7:0] Q;
wire Q1Q2Q3;
wire N_1;
supply0 GND;
wire UCTCO;
supply1 VCC;

mux2x2 I_60 ( .A(GND), .B(Q[0]), .Q(N_1), .S(Q1Q2Q3) );
dffc I_61 ( .CLK(CLK), .CLR(CLR), .D(N_1), .Q(UCTCO) );
and3i0 I_17 ( .A(Q[1]), .B(Q[2]), .C(Q[3]), .Q(Q1Q2Q3) );
ucebit2a UCT4 ( .CLK(CLK), .CLR(CLR), .ENH1(UCTCO), .ENH2(VCC), .ENH3(VCC),
             .ENH4(VCC), .ENL1(GND), .ENL2(GND), .ENL3(GND), .Q(Q[4]),
             .QFB(Q[4]) );
ucebit2a UCT0 ( .CLK(CLK), .CLR(CLR), .ENH1(VCC), .ENH2(VCC), .ENH3(VCC),
             .ENH4(VCC), .ENL1(GND), .ENL2(GND), .ENL3(GND), .Q(Q[0]),
             .QFB(Q[0]) );
ucebit2a UCT7 ( .CLK(CLK), .CLR(CLR), .ENH1(Q[4]), .ENH2(Q[5]), .ENH3(Q[6]),
             .ENH4(UCTCO), .ENL1(GND), .ENL2(GND), .ENL3(GND), .Q(Q[7]),
             .QFB(Q[7]) );
ucebit2a UCT6 ( .CLK(CLK), .CLR(CLR), .ENH1(Q[4]), .ENH2(Q[5]), .ENH3(UCTCO),
             .ENH4(VCC), .ENL1(GND), .ENL2(GND), .ENL3(GND), .Q(Q[6]),
             .QFB(Q[6]) );
ucebit2a UCT5 ( .CLK(CLK), .CLR(CLR), .ENH1(Q[4]), .ENH2(UCTCO), .ENH3(VCC),
             .ENH4(VCC), .ENL1(GND), .ENL2(GND), .ENL3(GND), .Q(Q[5]),
             .QFB(Q[5]) );
ucebit2a UCT3 ( .CLK(CLK), .CLR(CLR), .ENH1(Q[0]), .ENH2(Q[1]), .ENH3(Q[2]),
             .ENH4(VCC), .ENL1(GND), .ENL2(GND), .ENL3(GND), .Q(Q[3]),
             .QFB(Q[3]) );
ucebit2a UCT2 ( .CLK(CLK), .CLR(CLR), .ENH1(Q[0]), .ENH2(Q[1]), .ENH3(VCC),
             .ENH4(VCC), .ENL1(GND), .ENL2(GND), .ENL3(GND), .Q(Q[2]),
             .QFB(Q[2]) );
ucebit2a UCT1 ( .CLK(CLK), .CLR(CLR), .ENH1(Q[0]), .ENH2(VCC), .ENH3(VCC),
             .ENH4(VCC), .ENL1(GND), .ENL2(GND), .ENL3(GND), .Q(Q[1]),
             .QFB(Q[1]) );

endmodule // uct8p2

`endif

`ifdef tpad8_25um
`else
`define tpad8_25um
module tpad8_25um( A , EN, P );
 input [7:0] A;
input EN;
 output [7:0] P;

tripad_25um I1 ( .A(A[0]), .EN(EN), .P(P[0]) );
tripad_25um I2 ( .A(A[1]), .EN(EN), .P(P[1]) );
tripad_25um I3 ( .A(A[2]), .EN(EN), .P(P[2]) );
tripad_25um I4 ( .A(A[3]), .EN(EN), .P(P[3]) );
tripad_25um I5 ( .A(A[4]), .EN(EN), .P(P[4]) );
tripad_25um I6 ( .A(A[5]), .EN(EN), .P(P[5]) );
tripad_25um I7 ( .A(A[6]), .EN(EN), .P(P[6]) );
tripad_25um I8 ( .A(A[7]), .EN(EN), .P(P[7]) );

endmodule // tpad8_25um

`endif

`ifdef tpad8ff_25um
`else
`define tpad8ff_25um
module tpad8ff_25um( A , EN, FFCLK, FFCLR, P, Q );
 input [7:0] A;
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input EN;
 output [7:0] P;
 output [7:0] Q;

tripadff_25um I4 ( .A(A[3]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[3]),
                .Q(Q[3]) );
tripadff_25um I3 ( .A(A[2]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[2]),
                .Q(Q[2]) );
tripadff_25um I2 ( .A(A[1]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[1]),
                .Q(Q[1]) );
tripadff_25um I1 ( .A(A[0]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[0]),
                .Q(Q[0]) );
tripadff_25um I5 ( .A(A[4]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[4]),
                .Q(Q[4]) );
tripadff_25um I6 ( .A(A[5]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[5]),
                .Q(Q[5]) );
tripadff_25um I7 ( .A(A[6]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[6]),
                .Q(Q[6]) );
tripadff_25um I8 ( .A(A[7]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[7]),
                .Q(Q[7]) );

endmodule // tpad8ff_25um

`endif

`ifdef tpad4ff_25um
`else
`define tpad4ff_25um
module tpad4ff_25um( A , EN, FFCLK, FFCLR, P, Q );
 input [3:0] A;
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input EN;
 output [3:0] P;
 output [3:0] Q;

tripadff_25um I1 ( .A(A[0]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[0]),
                .Q(Q[0]) );
tripadff_25um I2 ( .A(A[1]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[1]),
                .Q(Q[1]) );
tripadff_25um I3 ( .A(A[2]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[2]),
                .Q(Q[2]) );
tripadff_25um I4 ( .A(A[3]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[3]),
                .Q(Q[3]) );

endmodule // tpad4ff_25um

`endif

`ifdef tpad4_25um
`else
`define tpad4_25um
module tpad4_25um( A , EN, P );
 input [3:0] A;
input EN;
 output [3:0] P;

tripad_25um I1 ( .A(A[0]), .EN(EN), .P(P[0]) );
tripad_25um I2 ( .A(A[1]), .EN(EN), .P(P[1]) );
tripad_25um I3 ( .A(A[2]), .EN(EN), .P(P[2]) );
tripad_25um I4 ( .A(A[3]), .EN(EN), .P(P[3]) );

endmodule // tpad4_25um

`endif

`ifdef tpad16ff_25um
`else
`define tpad16ff_25um
module tpad16ff_25um( A , EN, FFCLK, FFCLR, P, Q );
 input [15:0] A;
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
input EN;
 output [15:0] P;
 output [15:0] Q;

tripadff_25um I1 ( .A(A[0]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[0]),
                .Q(Q[0]) );
tripadff_25um I2 ( .A(A[1]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[1]),
                .Q(Q[1]) );
tripadff_25um I3 ( .A(A[2]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[2]),
                .Q(Q[2]) );
tripadff_25um I10 ( .A(A[3]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[3]),
                 .Q(Q[3]) );
tripadff_25um I4 ( .A(A[4]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[4]),
                .Q(Q[4]) );
tripadff_25um I5 ( .A(A[5]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[5]),
                .Q(Q[5]) );
tripadff_25um I6 ( .A(A[6]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[6]),
                .Q(Q[6]) );
tripadff_25um I11 ( .A(A[7]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[7]),
                 .Q(Q[7]) );
tripadff_25um I7 ( .A(A[8]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[8]),
                .Q(Q[8]) );
tripadff_25um I8 ( .A(A[9]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[9]),
                .Q(Q[9]) );
tripadff_25um I9 ( .A(A[10]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[10]),
                .Q(Q[10]) );
tripadff_25um I12 ( .A(A[11]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[11]),
                 .Q(Q[11]) );
tripadff_25um I13 ( .A(A[12]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[12]),
                 .Q(Q[12]) );
tripadff_25um I14 ( .A(A[13]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[13]),
                 .Q(Q[13]) );
tripadff_25um I15 ( .A(A[14]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[14]),
                 .Q(Q[14]) );
tripadff_25um I16 ( .A(A[15]), .EN(EN), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[15]),
                 .Q(Q[15]) );

endmodule // tpad16ff_25um

`endif

`ifdef tpad16_25um
`else
`define tpad16_25um
module tpad16_25um( A , EN, P );
 input [15:0] A;
input EN;
 output [15:0] P;

tripad_25um I1 ( .A(A[0]), .EN(EN), .P(P[0]) );
tripad_25um I2 ( .A(A[1]), .EN(EN), .P(P[1]) );
tripad_25um I3 ( .A(A[2]), .EN(EN), .P(P[2]) );
tripad_25um I4 ( .A(A[3]), .EN(EN), .P(P[3]) );
tripad_25um I5 ( .A(A[4]), .EN(EN), .P(P[4]) );
tripad_25um I6 ( .A(A[5]), .EN(EN), .P(P[5]) );
tripad_25um I7 ( .A(A[6]), .EN(EN), .P(P[6]) );
tripad_25um I8 ( .A(A[7]), .EN(EN), .P(P[7]) );
tripad_25um I9 ( .A(A[8]), .EN(EN), .P(P[8]) );
tripad_25um I10 ( .A(A[9]), .EN(EN), .P(P[9]) );
tripad_25um I11 ( .A(A[10]), .EN(EN), .P(P[10]) );
tripad_25um I12 ( .A(A[11]), .EN(EN), .P(P[11]) );
tripad_25um I13 ( .A(A[12]), .EN(EN), .P(P[12]) );
tripad_25um I14 ( .A(A[13]), .EN(EN), .P(P[13]) );
tripad_25um I15 ( .A(A[14]), .EN(EN), .P(P[14]) );
tripad_25um I16 ( .A(A[15]), .EN(EN), .P(P[15]) );

endmodule // tpad16_25um

`endif

`ifdef opad8ff_25um
`else
`define opad8ff_25um
module opad8ff_25um( A , FFCLK, FFCLR, P, P_FB );
 input [7:0] A;
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
 output [7:0] P;
 output [7:0] P_FB;

outpadff_25um I1 ( .A(A[0]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[0]),
                .P_FB(P_FB[0]) );
outpadff_25um I2 ( .A(A[1]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[1]),
                .P_FB(P_FB[1]) );
outpadff_25um I3 ( .A(A[2]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[2]),
                .P_FB(P_FB[2]) );
outpadff_25um I4 ( .A(A[3]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[3]),
                .P_FB(P_FB[3]) );
outpadff_25um I5 ( .A(A[4]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[4]),
                .P_FB(P_FB[4]) );
outpadff_25um I6 ( .A(A[5]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[5]),
                .P_FB(P_FB[5]) );
outpadff_25um I7 ( .A(A[6]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[6]),
                .P_FB(P_FB[6]) );
outpadff_25um I8 ( .A(A[7]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[7]),
                .P_FB(P_FB[7]) );

endmodule // opad8ff_25um

`endif

`ifdef opad8_25um
`else
`define opad8_25um
module opad8_25um( A , P );
 input [7:0] A;
 output [7:0] P;

outpad_25um I1 ( .A(A[0]), .P(P[0]) );
outpad_25um I2 ( .A(A[1]), .P(P[1]) );
outpad_25um I3 ( .A(A[2]), .P(P[2]) );
outpad_25um I4 ( .A(A[3]), .P(P[3]) );
outpad_25um I5 ( .A(A[4]), .P(P[4]) );
outpad_25um I6 ( .A(A[5]), .P(P[5]) );
outpad_25um I7 ( .A(A[6]), .P(P[6]) );
outpad_25um I8 ( .A(A[7]), .P(P[7]) );

endmodule // opad8_25um

`endif

`ifdef opad4ff_25um
`else
`define opad4ff_25um
module opad4ff_25um( A , FFCLK, FFCLR, P, P_FB );
 input [3:0] A;
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR /* synthesis syn_isclock=1 */;
 output [3:0] P;
 output [3:0] P_FB;

outpadff_25um I1 ( .A(A[0]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[0]),
                .P_FB(P_FB[0]) );
outpadff_25um I2 ( .A(A[1]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[1]),
                .P_FB(P_FB[1]) );
outpadff_25um I3 ( .A(A[2]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[2]),
                .P_FB(P_FB[2]) );
outpadff_25um I4 ( .A(A[3]), .FFCLK(FFCLK), .FFCLR(FFCLR), .P(P[3]),
                .P_FB(P_FB[3]) );

endmodule // opad4ff_25um

`endif

`ifdef opad4_25um
`else
`define opad4_25um
module opad4_25um( A , P );
 input [3:0] A;
 output [3:0] P;