📄 macros.v
字号:
/* Verilog Model Created from SCS Schematic macros.sch */
/* From: Sandya@quicklogic.com */
/* Date: August 31, 2001 */
/* Revision: 1.1 */
/* 8/31/01 Added Synthesis attributes (syn_isclock=1 and black_box_tri_pin)
for rev1.1 (sandya) */
/* If you are simulating a 0.25 micron device, you should copy
'macros-25.v' to 'macros.v' before starting simulation. */
/* If you are simulating pre-0.25 micron devices, you should copy
'macros-original.v' to 'macros.v' before starting simulation. */
/* Automatically generated by hvveri version 9.1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR 2
`define INCELL 3
`define CLOCK 4
`define HSCK 5
`define CLOCKB 6
`define ESPXCLKIN 7
`define HSCKMUX 8
`define IOCONTROL 9
`ifdef upflct32
`else
`define upflct32
module upflct32( CLK , CLR, D, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:31] D;
input LOAD;
output [0:31] Q;
wire N_1;
wire N_2;
wire N_3;
wire N_4;
wire N_5;
wire N_6;
wire N_7;
wire N_8;
wire N_9;
wire N_10;
wire N_11;
wire N_12;
wire N_13;
wire N_14;
upflct4a QL11 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .LOAD(LOAD), .Q({ Q[0:3] }),
.RCO(N_14) );
upflct4b QL10 ( .CLK(CLK), .CLR(CLR), .D({ D[20:23] }), .ENP(N_7), .ENT(N_11),
.LOAD(LOAD), .Q({ Q[20:23] }), .RCO(N_12) );
upflct4b QL9 ( .CLK(CLK), .CLR(CLR), .D({ D[24:27] }), .ENP(N_4), .ENT(N_12),
.LOAD(LOAD), .Q({ Q[24:27] }), .RCO(N_13) );
upflct4b QL8 ( .CLK(CLK), .CLR(CLR), .D({ D[16:19] }), .ENP(N_3), .ENT(N_10),
.LOAD(LOAD), .Q({ Q[16:19] }), .RCO(N_11) );
upflct4b QL7 ( .CLK(CLK), .CLR(CLR), .D({ D[12:15] }), .ENP(N_6), .ENT(N_9),
.LOAD(LOAD), .Q({ Q[12:15] }), .RCO(N_10) );
upflct4b QL6 ( .CLK(CLK), .CLR(CLR), .D({ D[8:11] }), .ENP(N_2), .ENT(N_8),
.LOAD(LOAD), .Q({ Q[8:11] }), .RCO(N_9) );
upflct4b QL5 ( .CLK(CLK), .CLR(CLR), .D({ D[4:7] }), .ENP(N_5), .ENT(N_14),
.LOAD(LOAD), .Q({ Q[4:7] }), .RCO(N_8) );
upflct4c QL4 ( .CLK(CLK), .CLR(CLR), .D({ D[28:31] }), .ENP(N_1), .ENT(N_13),
.LOAD(LOAD), .Q({ Q[28:31] }) );
upflcar2 QL3 ( .ACO1(N_6), .ACO2(N_3), .CLK(CLK), .CLR(CLR), .D({ D[0:1] }),
.LOAD(LOAD) );
upflcar2 QL2 ( .ACO1(N_5), .ACO2(N_2), .CLK(CLK), .CLR(CLR), .D({ D[0:1] }),
.LOAD(LOAD) );
upflcar3 QL1 ( .ACO1(N_7), .ACO2(N_4), .ACO3(N_1), .CLK(CLK), .CLR(CLR),
.D({ D[0:1] }), .LOAD(LOAD) );
endmodule // upflct32
`endif
`ifdef upfxct8
`else
`define upfxct8
module upfxct8( CLK , CLR, D, EN, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:7] D;
input EN, LOAD;
output [0:7] Q;
wire N_1;
wire N_2;
upfxcar1 QL3 ( .ACO1(N_1), .CLK(CLK), .CLR(CLR), .D({ D[0:1] }), .ENG(EN),
.LOAD(LOAD), .Q({ Q[0:1] }) );
upfxct4c QL2 ( .CLK(CLK), .CLR(CLR), .D({ D[4:7] }), .ENG(EN), .ENP(N_1),
.ENT(N_2), .LOAD(LOAD), .Q({ Q[4:7] }) );
upfxct4a QL1 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .ENG(EN), .LOAD(LOAD),
.Q({ Q[0:3] }), .RCO(N_2) );
endmodule // upfxct8
`endif
`ifdef upfxct4
`else
`define upfxct4
module upfxct4( CLK , CLR, D, EN, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:3] D;
input EN, LOAD;
output [0:3] Q;
supply0 GND;
upfxct4c QL1 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .ENG(EN), .ENP(GND),
.ENT(GND), .LOAD(LOAD), .Q({ Q[0:3] }) );
endmodule // upfxct4
`endif
`ifdef upfxct32
`else
`define upfxct32
module upfxct32( CLK , CLR, D, EN, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:31] D;
input EN, LOAD;
output [0:31] Q;
wire N_1;
wire N_2;
wire N_3;
wire N_4;
wire N_5;
wire N_6;
wire N_7;
wire N_8;
wire N_9;
wire N_10;
wire N_11;
wire N_12;
wire N_13;
wire N_14;
upfxct4c QL11 ( .CLK(CLK), .CLR(CLR), .D({ D[28:31] }), .ENG(EN), .ENP(N_1),
.ENT(N_4), .LOAD(LOAD), .Q({ Q[28:31] }) );
upfxcar3 QL10 ( .ACO1(N_11), .ACO2(N_10), .ACO3(N_9), .CLK(CLK), .CLR(CLR),
.D({ D[0:1] }), .ENG(EN), .LOAD(LOAD), .Q({ Q[0:1] }) );
upfxcar2 QL9 ( .ACO1(N_2), .ACO2(N_1), .CLK(CLK), .CLR(CLR), .D({ D[0:1] }),
.ENG(EN), .LOAD(LOAD) );
upfxcar2 QL8 ( .ACO1(N_6), .ACO2(N_5), .CLK(CLK), .CLR(CLR), .D({ D[0:1] }),
.ENG(EN), .LOAD(LOAD) );
upfxct4a QL7 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .ENG(EN), .LOAD(LOAD),
.Q({ Q[0:3] }), .RCO(N_14) );
upfxct4b QL6 ( .CLK(CLK), .CLR(CLR), .D({ D[24:27] }), .ENG(EN), .ENP(N_2),
.ENT(N_3), .LOAD(LOAD), .Q({ Q[24:27] }), .RCO(N_4) );
upfxct4b QL5 ( .CLK(CLK), .CLR(CLR), .D({ D[20:23] }), .ENG(EN), .ENP(N_5),
.ENT(N_8), .LOAD(LOAD), .Q({ Q[20:23] }), .RCO(N_3) );
upfxct4b QL4 ( .CLK(CLK), .CLR(CLR), .D({ D[16:19] }), .ENG(EN), .ENP(N_6),
.ENT(N_7), .LOAD(LOAD), .Q({ Q[16:19] }), .RCO(N_8) );
upfxct4b QL3 ( .CLK(CLK), .CLR(CLR), .D({ D[12:15] }), .ENG(EN), .ENP(N_9),
.ENT(N_13), .LOAD(LOAD), .Q({ Q[12:15] }), .RCO(N_7) );
upfxct4b QL2 ( .CLK(CLK), .CLR(CLR), .D({ D[8:11] }), .ENG(EN), .ENP(N_10),
.ENT(N_12), .LOAD(LOAD), .Q({ Q[8:11] }), .RCO(N_13) );
upfxct4b QL1 ( .CLK(CLK), .CLR(CLR), .D({ D[4:7] }), .ENG(EN), .ENP(N_11),
.ENT(N_14), .LOAD(LOAD), .Q({ Q[4:7] }), .RCO(N_12) );
endmodule // upfxct32
`endif
`ifdef upfxct24
`else
`define upfxct24
module upfxct24( CLK , CLR, D, EN, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:23] D;
input EN, LOAD;
output [0:23] Q;
wire N_1;
wire N_2;
wire N_3;
wire N_4;
wire N_5;
wire N_6;
wire N_7;
wire N_8;
wire N_9;
wire N_10;
upfxct4c QL8 ( .CLK(CLK), .CLR(CLR), .D({ D[20:23] }), .ENG(EN), .ENP(N_1),
.ENT(N_3), .LOAD(LOAD), .Q({ Q[20:23] }) );
upfxcar3 QL7 ( .ACO1(N_7), .ACO2(N_6), .ACO3(N_5), .CLK(CLK), .CLR(CLR),
.D({ D[0:1] }), .ENG(EN), .LOAD(LOAD), .Q({ Q[0:1] }) );
upfxcar2 QL6 ( .ACO1(N_2), .ACO2(N_1), .CLK(CLK), .CLR(CLR), .D({ D[0:1] }),
.ENG(EN), .LOAD(LOAD) );
upfxct4a QL5 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .ENG(EN), .LOAD(LOAD),
.Q({ Q[0:3] }), .RCO(N_10) );
upfxct4b QL4 ( .CLK(CLK), .CLR(CLR), .D({ D[16:19] }), .ENG(EN), .ENP(N_2),
.ENT(N_4), .LOAD(LOAD), .Q({ Q[16:19] }), .RCO(N_3) );
upfxct4b QL3 ( .CLK(CLK), .CLR(CLR), .D({ D[12:15] }), .ENG(EN), .ENP(N_5),
.ENT(N_9), .LOAD(LOAD), .Q({ Q[12:15] }), .RCO(N_4) );
upfxct4b QL2 ( .CLK(CLK), .CLR(CLR), .D({ D[8:11] }), .ENG(EN), .ENP(N_6),
.ENT(N_8), .LOAD(LOAD), .Q({ Q[8:11] }), .RCO(N_9) );
upfxct4b QL1 ( .CLK(CLK), .CLR(CLR), .D({ D[4:7] }), .ENG(EN), .ENP(N_7),
.ENT(N_10), .LOAD(LOAD), .Q({ Q[4:7] }), .RCO(N_8) );
endmodule // upfxct24
`endif
`ifdef upfxct16
`else
`define upfxct16
module upfxct16( CLK , CLR, D, EN, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:15] D;
input EN, LOAD;
output [0:15] Q;
wire N_1;
wire N_2;
wire N_3;
wire N_4;
wire N_5;
wire N_6;
upfxcar3 QL5 ( .ACO1(N_3), .ACO2(N_2), .ACO3(N_1), .CLK(CLK), .CLR(CLR),
.D({ D[0:1] }), .ENG(EN), .LOAD(LOAD), .Q({ Q[0:1] }) );
upfxct4c QL4 ( .CLK(CLK), .CLR(CLR), .D({ D[12:15] }), .ENG(EN), .ENP(N_1),
.ENT(N_5), .LOAD(LOAD), .Q({ Q[12:15] }) );
upfxct4b QL3 ( .CLK(CLK), .CLR(CLR), .D({ D[8:11] }), .ENG(EN), .ENP(N_2),
.ENT(N_4), .LOAD(LOAD), .Q({ Q[8:11] }), .RCO(N_5) );
upfxct4b QL2 ( .CLK(CLK), .CLR(CLR), .D({ D[4:7] }), .ENG(EN), .ENP(N_3),
.ENT(N_6), .LOAD(LOAD), .Q({ Q[4:7] }), .RCO(N_4) );
upfxct4a QL1 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .ENG(EN), .LOAD(LOAD),
.Q({ Q[0:3] }), .RCO(N_6) );
endmodule // upfxct16
`endif
`ifdef upflct8
`else
`define upflct8
module upflct8( CLK , CLR, D, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:7] D;
input LOAD;
output [0:7] Q;
wire N_1;
supply0 GND;
upflcar1 QL3 ( .ACO1(N_1), .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .LOAD(LOAD),
.Q({ Q[0:3] }) );
upflct4c QL2 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .ENP(GND), .ENT(GND),
.LOAD(LOAD), .Q({ Q[0:3] }) );
upflct4c QL1 ( .CLK(CLK), .CLR(CLR), .D({ D[4:7] }), .ENP(N_1), .ENT(GND),
.LOAD(LOAD), .Q({ Q[4:7] }) );
endmodule // upflct8
`endif
`ifdef upflct4
`else
`define upflct4
module upflct4( CLK , CLR, D, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:3] D;
input LOAD;
output [0:3] Q;
supply0 GND;
upflct4c QL1 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .ENP(GND), .ENT(GND),
.LOAD(LOAD), .Q({ Q[0:3] }) );
endmodule // upflct4
`endif
`ifdef upflct24
`else
`define upflct24
module upflct24( CLK , CLR, D, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:23] D;
input LOAD;
output [0:23] Q;
wire N_1;
wire N_2;
wire N_3;
wire N_4;
wire N_5;
wire N_6;
wire N_7;
wire N_8;
wire N_9;
wire N_10;
upflct4a QL8 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .LOAD(LOAD), .Q({ Q[0:3] }),
.RCO(N_10) );
upflct4b QL7 ( .CLK(CLK), .CLR(CLR), .D({ D[16:19] }), .ENP(N_2), .ENT(N_4),
.LOAD(LOAD), .Q({ Q[16:19] }), .RCO(N_5) );
upflct4b QL6 ( .CLK(CLK), .CLR(CLR), .D({ D[12:15] }), .ENP(N_3), .ENT(N_9),
.LOAD(LOAD), .Q({ Q[12:15] }), .RCO(N_4) );
upflct4b QL5 ( .CLK(CLK), .CLR(CLR), .D({ D[8:11] }), .ENP(N_6), .ENT(N_8),
.LOAD(LOAD), .Q({ Q[8:11] }), .RCO(N_9) );
upflct4b QL4 ( .CLK(CLK), .CLR(CLR), .D({ D[4:7] }), .ENP(N_7), .ENT(N_10),
.LOAD(LOAD), .Q({ Q[4:7] }), .RCO(N_8) );
upflct4c QL3 ( .CLK(CLK), .CLR(CLR), .D({ D[20:23] }), .ENP(N_1), .ENT(N_5),
.LOAD(LOAD), .Q({ Q[20:23] }) );
upflcar2 QL2 ( .ACO1(N_7), .ACO2(N_6), .CLK(CLK), .CLR(CLR), .D({ D[0:1] }),
.LOAD(LOAD) );
upflcar3 QL1 ( .ACO1(N_3), .ACO2(N_2), .ACO3(N_1), .CLK(CLK), .CLR(CLR),
.D({ D[0:1] }), .LOAD(LOAD) );
endmodule // upflct24
`endif
`ifdef upflct16
`else
`define upflct16
module upflct16( CLK , CLR, D, LOAD, Q );
input CLK /* synthesis syn_isclock=1 */;
input CLR /* synthesis syn_isclock=1 */;
input [0:15] D;
input LOAD;
output [0:15] Q;
wire N_1;
wire N_2;
wire N_3;
wire N_4;
wire N_5;
wire N_6;
upflct4a QL5 ( .CLK(CLK), .CLR(CLR), .D({ D[0:3] }), .LOAD(LOAD), .Q({ Q[0:3] }),
.RCO(N_6) );
upflct4b QL4 ( .CLK(CLK), .CLR(CLR), .D({ D[8:11] }), .ENP(N_2), .ENT(N_4),
.LOAD(LOAD), .Q({ Q[8:11] }), .RCO(N_5) );
upflct4b QL3 ( .CLK(CLK), .CLR(CLR), .D({ D[4:7] }), .ENP(N_3), .ENT(N_6),
.LOAD(LOAD), .Q({ Q[4:7] }), .RCO(N_4) );
upflct4c QL2 ( .CLK(CLK), .CLR(CLR), .D({ D[12:15] }), .ENP(N_1), .ENT(N_5),
.LOAD(LOAD), .Q({ Q[12:15] }) );
upflcar3 QL1 ( .ACO1(N_3), .ACO2(N_2), .ACO3(N_1), .CLK(CLK), .CLR(CLR),
.D({ D[0:1] }), .LOAD(LOAD) );
endmodule // upflct16
`endif
`ifdef reg_lvpecl_outpad_25dc
`else
`define reg_lvpecl_outpad_25dc
module reg_lvpecl_outpad_25dc( clk , clr, input2diff, Vo_neg, Vo_pos );
input clk /* synthesis syn_isclock=1 */;
input clr /* synthesis syn_isclock=1 */;
input input2diff;
output Vo_neg, Vo_pos;
wire inv;
wire non_inv;
supply1 vcc;
supply0 gnd;
super_logic I4 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
.B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
.E1(gnd), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
.F5(vcc), .F6(gnd), .MP(input2diff), .MS(gnd), .NP(input2diff),
.NS(gnd), .NZ(inv), .OP(gnd), .OS(gnd), .OZ(non_inv), .PP(vcc),
.PS(gnd), .QC(gnd), .QR(gnd), .QS(vcc) );
outpadff_25um I1 ( .A(inv), .FFCLK(clk), .FFCLR(clr), .P(Vo_neg) );
outpadff_25um I2 ( .A(non_inv), .FFCLK(clk), .FFCLR(clr), .P(Vo_pos) );
endmodule // reg_lvpecl_outpad_25dc
`endif
`ifdef reg_lvpecl_outpad_25ac
`else
`define reg_lvpecl_outpad_25ac
module reg_lvpecl_outpad_25ac( clk , clr, input2diff, Vo_neg, Vo_pos );
input input2diff;
input clk /* synthesis syn_isclock=1 */;
input clr /* synthesis syn_isclock=1 */;
output Vo_neg, Vo_pos;
wire inv;
wire non_inv;
supply1 vcc;
supply0 gnd;
eio_25um I8 ( .A2(gnd), .EN(vcc), .FFCLK(clk), .FFCLR(clr), .I_EN(gnd),
.OE_EN(non_inv), .OESEL(gnd), .OSEL(vcc), .P(Vo_neg) );
eio_25um I9 ( .A2(gnd), .EN(vcc), .FFCLK(clk), .FFCLR(clr), .I_EN(gnd),
.OE_EN(inv), .OESEL(gnd), .OSEL(vcc), .P(Vo_pos) );
super_logic I4 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
.B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
.E1(gnd), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
.F5(vcc), .F6(gnd), .MP(input2diff), .MS(gnd), .NP(input2diff),
.NS(gnd), .NZ(inv), .OP(gnd), .OS(gnd), .OZ(non_inv), .PP(vcc),
.PS(gnd), .QC(gnd), .QR(gnd), .QS(vcc) );
endmodule // reg_lvpecl_outpad_25ac
`endif
`ifdef lvpecl_outpad_25dc
`else
`define lvpecl_outpad_25dc
module lvpecl_outpad_25dc( input2diff , Vo_neg, Vo_pos );
input input2diff;
output Vo_neg, Vo_pos;
wire inv;
wire non_inv;
supply1 vcc;
supply0 gnd;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -