demo_amba.srr

appnote65_quickmips_ahb_interface_design_example AHB接口设计

$ Start of Compile
#Fri Sep 13 17:34:13 2002

Synplicity Verilog Compiler, version 7.0.0, Build 130R, built Nov 16 2001
Copyright (C) 1994-2001, Synplicity Inc.  All Rights Reserved

@I::"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\macros.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\ahb_master.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\ahb_slave.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\appreq_sm.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\app_codec.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\app_codec.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\xor32x2.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\qmipsesp.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\busreq_sm.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\fifo128x32.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\fifo128x32.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\r128a32_25um.v"
@I:"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\r128a32_25um.v":"\\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\ram128x18_25um.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module demo_amba
Synthesizing module qmipsesp
Synthesizing module hsckmux
Synthesizing module gclkbuff_25um
Synthesizing module ahb_master
@W:"\\Judd_ql_dallas\D\mips\ahb\interface_ex\verilog\ahb_master.v":196:0:196:5|Optimizing register bit hburst_o[1] to a constant 0
Synthesizing module busreq_sm
Synthesizing module RAM128X18_25UM
Synthesizing module r128a32_25um
Synthesizing module fifo128x32
Synthesizing module appreq_sm
Synthesizing module ahb_slave
@W:"\\Judd_ql_dallas\D\mips\ahb\interface_ex\verilog\ahb_slave.v":59:16:59:25|Input ahbs_hsize is unused
@W:"\\Judd_ql_dallas\D\mips\ahb\interface_ex\verilog\ahb_slave.v":60:16:60:26|Input ahbs_hburst is unused
@W:"\\Judd_ql_dallas\D\mips\ahb\interface_ex\verilog\ahb_slave.v":61:16:61:25|Input ahbs_hprot is unused
Synthesizing module frag_a
Synthesizing module frag_m
Synthesizing module frag_f
Synthesizing module xor2i0
Synthesizing module xor32x2
Synthesizing module app_codec
Synthesizing module demo_amba
@END
Process took 0.711 seconds realtime, 0.751 seconds cputime
Synplicity QuickLogic Technology Mapper, version 7.0.0, Build 129R, built Nov 12 2001
Copyright (C) 1994-2001, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 16
Loading Properties file: \\Judd_ql_dallas\d\mips\ahb\interface_ex\verilog_design\Synthesis_and_SpDE_files\demo_amba.sc
@N|Setting default wire load to 'pASICQDSP' 
@W:|Disconnecting duplicate driver pin:O[0] inst:true of PrimLib.true(prim)
@W:|Disconnecting duplicate driver pin:O[0] inst:false of PrimLib.false(prim)
Automatic dissolve at startup in view:work.fifo128x32(verilog) of m(r128a32_25um)
Automatic dissolve at startup in view:work.app_codec(verilog) of xor2_1(xor32x2)
Automatic dissolve at startup in view:work.demo_amba(verilog) of app_inst(app_codec)
Automatic dissolve at startup in view:work.demo_amba(verilog) of out_fifo(fifo128x32)
Automatic dissolve at startup in view:work.demo_amba(verilog) of in_fifo(fifo128x32)
@W:"\\judd_ql_dallas\d\mips\ahb\interface_ex\verilog\fifo128x32.v":68:16:68:27|Removing sequential instance I_168 of view:PrimLib.dffrs(prim) because there are no references to its outputs 
@W:"\\judd_ql_dallas\d\mips\ahb\interface_ex\verilog\fifo128x32.v":68:16:68:27|Removing sequential instance I_134 of view:PrimLib.dffrs(prim) because there are no references to its outputs 
@W:"\\judd_ql_dallas\d\mips\ahb\interface_ex\verilog\fifo128x32.v":68:16:68:27|Removing sequential instance I_100 of view:PrimLib.dffrs(prim) because there are no references to its outputs 
@W:"\\judd_ql_dallas\d\mips\ahb\interface_ex\verilog\fifo128x32.v":68:16:68:27|Removing sequential instance I_66 of view:PrimLib.dffrs(prim) because there are no references to its outputs 
@W:"\\judd_ql_dallas\d\mips\ahb\interface_ex\verilog\ahb_slave.v":146:0:146:5|Removing sequential instance curr_state[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:"\\judd_ql_dallas\d\mips\ahb\interface_ex\verilog\ahb_slave.v":130:0:130:5|Removing sequential instance prevsel[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
---------------------------------------
Resource Usage Report
Part: ql901m

Area estimate:  846 Cells
Register count: 247
Latch count:    0
I/O cells:      216

Details:
Q_INPAD_25UM:    53
Q_IOPAD_25UM:    76
Q_OUTPAD_25UM:   87

AND2I0:          73 (area 1)
AND2I1:          75 (area 1)
AND2I2:          32 (area 1)
AND3I0:           6 (area 1)
AND3I1:           5 (area 1)
AND3I2:           8 (area 1)
AND3I3:           9 (area 1)
AND4I1:           1 (area 1)
AND4I2:           3 (area 1)
AND4I3:           2 (area 1)
AND6I3:           3 (area 1)
LOGIC2:          26 (area 1)
MUX2X0:         101 (area 1)
MUX2X1:          95 (area 1)
MUX2X2:          22 (area 1)
MUX2X3:         112 (area 1)
OR2I0:           12 (area 1)
OR2I1:            8 (area 1)
OR2I2:            1 (area 1)
OR3I0:            4 (area 1)
OR3I1:            1 (area 1)
OR4I0:            6 (area 1)
OR5I1:            2 (area 1)
OR6I2:            1 (area 1)
Q_AND2:          67 (area 0.3)
Q_DECSKIP:        3 (area 1)
Q_DECSKIP2:       3 (area 1)
Q_DECX:          34 (area 1)
Q_DFF:          221
Q_INCSKIP:        7 (area 1)
Q_INCSKIP2:      10 (area 1)
Q_INCX:         108 (area 1)
Q_INV:           19 (area 0.2)
RAM128X18_25UM:   4
XNOR2I0:          4 (area 1)
XOR2I0:          12 (area 1)
gclkbuff_25um:    1 (area 1)
qmipsesp:         1
xor2i0:          32 (area 1)

@W:"\\judd_ql_dallas\d\mips\ahb\interface_ex\verilog\demo_amba.v":347:9:347:21|Net hclk appears to be a clock source which was not identified. Assuming default frequency. 


##### START TIMING REPORT #####
# Timing Report written on Fri Sep 13 17:34:23 2002
#


Top view:              demo_amba
Operating conditions:  TYP-7
Wire load model:       pASICQDSP
Slew propagation mode: worst
Paths requested:       5
Constraint File(s):    
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.



Performance Summary 
*******************


Worst slack in design: 985.223

                   Requested     Estimated     Requested     Estimated                 Clock 
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type  
---------------------------------------------------------------------------------------------
System             1.0 MHz       67.7 MHz      1000.000      14.777        985.223     system
=============================================================================================



Interface Information 
*********************



Input Ports: 

Port                Starting            User           Arrival     Required            
Name                Reference           Constraint     Time        Time         Slack  
                    Clock                                                              
---------------------------------------------------------------------------------------
BOOT[0]             System (rising)     NA             0.000       999.224      999.224
BOOT[1]             System (rising)     NA             0.000       999.224      999.224
CPU_BIGENDIAN       System (rising)     NA             0.000       999.224      999.224
CPU_EXTINT_n[0]     System (rising)     NA             0.000       999.224      999.224
CPU_EXTINT_n[1]     System (rising)     NA             0.000       999.224      999.224
CPU_EXTINT_n[2]     System (rising)     NA             0.000       999.224      999.224
CPU_EXTINT_n[3]     System (rising)     NA             0.000       999.224      999.224
CPU_EXTINT_n[4]     System (rising)     NA             0.000       999.224      999.224
CPU_EXTINT_n[5]     System (rising)     NA             0.000       999.224      999.224
CPU_EXTINT_n[6]     System (rising)     NA             0.000       999.224      999.224
DATA[0]             NA                  NA             NA          NA           NA     
DATA[1]             NA                  NA             NA          NA           NA     
DATA[2]             NA                  NA             NA          NA           NA     
DATA[3]             NA                  NA             NA          NA           NA     
DATA[4]             NA                  NA             NA          NA           NA     
DATA[5]             NA                  NA             NA          NA           NA     
DATA[6]             NA                  NA             NA          NA           NA     
DATA[7]             NA                  NA             NA          NA           NA     
DATA[8]             NA                  NA             NA          NA           NA     
DATA[9]             NA                  NA             NA          NA           NA     
DATA[10]            NA                  NA             NA          NA           NA     
DATA[11]            NA                  NA             NA          NA           NA     
DATA[12]            NA                  NA             NA          NA           NA     
DATA[13]            NA                  NA             NA          NA           NA     
DATA[14]            NA                  NA             NA          NA           NA     
DATA[15]            NA                  NA             NA          NA           NA     
DATA[16]            NA                  NA             NA          NA           NA     
DATA[17]            NA                  NA             NA          NA           NA     
DATA[18]            NA                  NA             NA          NA           NA     
DATA[19]            NA                  NA             NA          NA           NA     
DATA[20]            NA                  NA             NA          NA           NA     
DATA[21]            NA                  NA             NA          NA           NA     
DATA[22]            NA                  NA             NA          NA           NA