demo_amba.qdf

appnote65_quickmips_ahb_interface_design_example AHB接口设计

  gate ahb_master.haddr_reg_11_0[27] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[27] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[26] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[26] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[25] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[25] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[24] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[24] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[23] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[23] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[22] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[22] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[21] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[21] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[20] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[20] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[19] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[19] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[18] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[18] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[17] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[17] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[16] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[16] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[15] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[15] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[14] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[14] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[13] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[13] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[12] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[12] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[11] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[11] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[10] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[10] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[9] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[9] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[8] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[8] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[7] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[7] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[6] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[6] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[5] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[5] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[4] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[4] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[3] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[3] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[2] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[2] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[1] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[1] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[0] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[0] master Q_MUX2X1 end
  gate ahb_master.un1_hburst_o34_2 master Q_AND2I1 end
  gate ahb_master.un1_un1_hwrite_o master Q_AND2I1 end
  gate ahb_master.un1_hburst_o60_1 master Q_AND2I1 end
  gate ahb_master.rddf_wren56 master Q_AND2I1 end
  gate ahb_master.un1_hburst_o63 master Q_AND2I1 end
  gate ahb_master.un1_un1_hburst_o_1 master Q_AND2I1 end
  gate ahb_master.un1_un1_hburst_o_2 master Q_AND2I1 end
  gate ahb_master.un1_hburst_o61_6 master Q_AND2I1 end
  gate ahb_master.un1_lastbrstrd master Q_OR2I1 end
  gate ahb_master.un1_un1_hburst_o_i master Q_AND2I0 end
  gate ahb_master.un1_hburst_o61_7 master Q_AND3I2 end
  gate ahb_master.un1_hburst_o66_6 master Q_AND3I1 end
  gate ahb_master.ahm_busreq_reg43 master Q_AND2I1 end
  gate ahb_master.un1_hburst_o66_2 master Q_AND2I1 end
  gate ahb_master.un1_hburst_o61_8 master Q_AND3I1 end
  gate ahb_master.hburst_o62 master Q_AND3I1 end
  gate ahb_master.hburst_o60_hburst_o60_1 master Q_AND2I1 end
  gate ahb_master.hburst_o65_hburst_o65_1 master Q_AND2I1 end
  gate ahb_master.hwrite_o_6 master Q_AND2I1 end
  gate ahb_master.haddr_reg_11_sn.G_8_0_and3 master Q_AND2I2 end
  gate ahb_master.lastbrstrd_135 master Q_AND2I2 end
  gate ahb_master.lastbrstrd_136 master Q_AND2I1 end
  gate ahb_master.burstwrflag_last_n_3 master Q_AND4I2 pack end
  gate busreq_sm.nextstate_i_and2_1[1] master Q_AND2I1 end
  gate busreq_sm.G_34 master Q_AND2I1 end
  gate busreq_sm.G_33 master Q_AND2I2 end
  gate busreq_sm.nextstate_i_i_and2[0] master Q_AND3I2 end
  gate busreq_sm.wr_update_0_and2 master Q_AND2I1 end
  gate ahb_slave.un1_un1_un1_prevsel_1 master Q_AND2I2 end
  gate ahb_slave.un1_un1_un1_prevsel master Q_AND2I2 end
  gate ahb_slave.un1_rd_update_1 master Q_AND2I1 end
  gate out_fifo.last_op14_1 master Q_AND2I1 end
  gate busreq_sm.nextstate63 master Q_AND2I2 end
  gate in_fifo.last_op14_1 master Q_AND2I1 end
  gate appreq_sm.nextstate10 master Q_AND2I2 end
  gate in_fifo.last_op13 master Q_AND3I2 end
  gate in_fifo.rptr10 master Q_AND2I1 end
  gate in_fifo.last_op14 master Q_AND2I1 end
  gate ahb_master.rddf_wren36 master Q_AND3I2 end
  gate ahb_master.un10_pop master Q_AND2I2 end
  gate ahb_master.hburst_o69 master Q_AND3I2 end
  gate ahb_master.hburst_o61 master Q_AND2I1 end
  gate out_fifo.last_op13_166 master Q_AND2I2 end
  gate busreq_sm.nextstate_i_and2_0[1] master Q_AND3I2 end
  gate busreq_sm.G_31 master Q_AND2I1 end
  gate out_fifo.rptr10 master Q_AND2I1 end
  gate app_inst.wait_count_6[2] master Q_AND2I1 end
  gate app_inst.wait_count_6[1] master Q_AND2I1 end
  gate app_inst.wait_count_6[0] master Q_AND2I1 end
  gate appreq_sm.G_7 master Q_OR2I1 end
  gate appreq_sm.start_0_and3 master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[20] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[19] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[18] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[17] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[16] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[15] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[14] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[13] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[12] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[11] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[10] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[9] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[8] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[7] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[6] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[5] master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_2[4] master Q_AND2I1 end
  gate ahb_slave.dst_addr7 master Q_AND2I1 end
  gate ahb_slave.un1_un1_prevsel_2 master Q_AND3I2 end
  gate ahb_slave.dst_addr8 master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata_sn.G_7_0 master Q_OR2I2 end
  gate ahb_master.un24_latch_addr_1 master Q_AND2I2 end
  gate ahb_master.hburst_o64_hburst_o64_1 master Q_AND2I1 end
  gate ahb_master.hburst_o60_hburst_o60 master Q_AND2I1 end
  gate ahb_master.hburst_o64_hburst_o64 master Q_AND2I1 end
  gate ahb_master.htrans_o_sn.htrans_o_17.htrans_o_8 master Q_AND2I2 end
  gate ahb_master.hburst_o66_2 master Q_AND2I2 end
  gate ahb_master.hburst_o63 master Q_AND3I2 end
  gate ahb_master.hburst_o58 master Q_AND3I3 end
  gate ahb_master.un1_un1_un24_latch_addr master Q_OR3I1 end
  gate ahb_master.hburst_o67 master Q_AND3I1 end
  gate ahb_master.hburst_o65_hburst_o65 master Q_AND2I1 end
  gate ahb_master.htrans_o_sn.htrans_o_17.htrans_o_4 master Q_AND2I1 end
  gate I_184 master Q_INV end
  gate I_185 master Q_INV end
  gate I_186 master Q_INV end
  gate I_187 master Q_INV end
  gate I_188 master Q_INV end
  gate I_189 master Q_INV end
  gate I_190 master Q_INV end
  gate I_191 master Q_INV end
  gate I_192 master Q_INV end
  gate I_193 master Q_INV end
  gate I_194 master Q_INV end
  gate I_195 master Q_INV end
  gate I_196 master Q_INV end
  gate I_197 master Q_INV end
  gate I_198 master Q_INV end
  gate I_199 master Q_INV end
  gate I_200 master Q_INV end
  gate I_201 master Q_INV end
  gate I_202 master Q_INV end
  gate ahb_master.haddr_reg[25] master Q_DFF end
  gate ahb_master.haddr_reg[26] master Q_DFF end
  gate ahb_master.haddr_reg[27] master Q_DFF end
  gate ahb_master.haddr_reg[28] master Q_DFF end
  gate ahb_master.haddr_reg[29] master Q_DFF end
  gate ahb_master.ahb_master_state[0] master Q_DFF end
  gate ahb_master.ahb_master_state[1] master Q_DFF end
  gate ahb_master.ahb_master_state[2] master Q_DFF end
  gate ahb_master.ahb_master_state[3] master Q_DFF end
  gate ahb_master.haddr_reg[10] master Q_DFF end
  gate ahb_master.haddr_reg[11] master Q_DFF end
  gate ahb_master.haddr_reg[12] master Q_DFF end
  gate ahb_master.haddr_reg[13] master Q_DFF end
  gate ahb_master.haddr_reg[14] master Q_DFF end
  gate ahb_master.haddr_reg[15] master Q_DFF end
  gate ahb_master.haddr_reg[16] master Q_DFF end
  gate ahb_master.haddr_reg[17] master Q_DFF end
  gate ahb_master.haddr_reg[18] master Q_DFF end
  gate ahb_master.haddr_reg[19] master Q_DFF end
  gate ahb_master.haddr_reg[20] master Q_DFF end
  gate ahb_master.haddr_reg[21] master Q_DFF end
  gate ahb_master.haddr_reg[22] master Q_DFF end
  gate ahb_master.haddr_reg[23] master Q_DFF end
  gate ahb_master.haddr_reg[24] master Q_DFF end
  gate ahb_master.word_count[0] master Q_DFF end
  gate ahb_master.word_count[1] master Q_DFF end
  gate ahb_master.word_count[2] master Q_DFF end
  gate ahb_master.word_count[3] master Q_DFF end
  gate ahb_master.word_count[4] master Q_DFF end
  gate ahb_master.haddr_reg[0] master Q_DFF end
  gate ahb_master.haddr_reg[1] master Q_DFF end
  gate ahb_master.haddr_reg[2] master Q_DFF end
  gate ahb_master.haddr_reg[3] master Q_DFF end
  gate ahb_master.haddr_reg[4] master Q_DFF end
  gate ahb_master.haddr_reg[5] master Q_DFF end
  gate ahb_master.haddr_reg[6] master Q_DFF end
  gate ahb_master.haddr_reg[7] master Q_DFF end
  gate ahb_master.haddr_reg[8] master Q_DFF end
  gate ahb_master.haddr_reg[9] master Q_DFF end
  gate ahb_master.hwdata_o[17] master Q_DFF end
  gate ahb_master.hwdata_o[18] master Q_DFF end
  gate ahb_master.hwdata_o[19] master Q_DFF end
  gate ahb_master.hwdata_o[20] master Q_DFF end
  gate ahb_master.hwdata_o[21] master Q_DFF end
  gate ahb_master.hwdata_o[22] master Q_DFF end
  gate ahb_master.hwdata_o[23] master Q_DFF end
  gate ahb_master.hwdata_o[24] master Q_DFF end
  gate ahb_master.hwdata_o[25] master Q_DFF end
  gate ahb_master.hwdata_o[26] master Q_DFF end
  gate ahb_master.hwdata_o[27] master Q_DFF end
  gate ahb_master.hwdata_o[28] master Q_DFF end
  gate ahb_master.hwdata_o[29] master Q_DFF end
  gate ahb_master.hwdata_o[30] master Q_DFF end
  gate ahb_master.hwdata_o[31] master Q_DFF end
  gate ahb_master.hwdata_o[2] master Q_DFF end
  gate ahb_master.hwdata_o[3] master Q_DFF end
  gate ahb_master.hwdata_o[4] master Q_DFF end
  gate ahb_master.hwdata_o[5] master Q_DFF end
  gate ahb_master.hwdata_o[6] master Q_DFF end
  gate ahb_master.hwdata_o[7] master Q_DFF end
  gate ahb_master.hwdata_o[8] master Q_DFF end
  gate ahb_master.hwdata_o[9] master Q_DFF end
  gate ahb_master.hwdata_o[10] master Q_DFF end
  gate ahb_master.hwdata_o[11] master Q_DFF end
  gate ahb_master.hwdata_o[12] master Q_DFF end
  gate ahb_master.hwdata_o[13] master Q_DFF end
  gate ahb_master.hwdata_o[14] master Q_DFF end
  gate ahb_master.hwdata_o[15] master Q_DFF end
  gate ahb_master.hwdata_o[16] master Q_DFF end
  gate appreq_sm.state[0] master Q_DFF end
  gate appreq_sm.state[1] master Q_DFF end
  gate busreq_sm.state[0] master Q_DFF end
  gate busreq_sm.state[1] master Q_DFF end
  gate busreq_sm.state[2] master Q_DFF end
  gate ahb_master.busreq_prev master Q_DFF end
  gate ahb_master.hbusreq_o master Q_DFF end
  gate ahb_master.rddf_wren master Q_DFF end
  gate ahb_master.hburst_o_1[0] master Q_DFF end
  gate ahb_master.burstwrflag_last_n master Q_DFF end
  gate ahb_master.hwrite_o master Q_DFF end
  gate ahb_master.latch_addr master Q_DFF end
  gate ahb_master.hwdata_o[0] master Q_DFF end
  gate ahb_master.hwdata_o[1] master Q_DFF end
  gate ahb_slave.dst_addr[31] master Q_DFF end
  gate ahb_slave.prevsel[1] master Q_DFF end
  gate ahb_slave.curr_state[1] master Q_DFF end
  gate ahb_slave.ahbs_haddr_reg[2] master Q_DFF end
  gate ahb_slave.ahbs_haddr_reg[3] master Q_DFF end
  gate ahb_slave.dst_addr[16] master Q_DFF end
  gate ahb_slave.dst_addr[17] master Q_DFF end
  gate ahb_slave.dst_addr[18] master Q_DFF end
  gate ahb_slave.dst_addr[19] master Q_DFF end
  gate ahb_slave.dst_addr[20] master Q_DFF end
  gate ahb_slave.dst_addr[21] master Q_DFF end
  gate ahb_slave.dst_addr[22] master Q_DFF end
  gate ahb_slave.dst_addr[23] master Q_DFF end
  gate ahb_slave.dst_addr[24] master Q_DFF end
  gate ahb_slave.dst_addr[25] master Q_DFF end
  gate ahb_slave.dst_addr[26] master Q_DFF end
  gate ahb_slave.dst_addr[27] master Q_DFF end
  gate ahb_slave.dst_addr[28] master Q_DFF end
  gate ahb_slave.dst_addr[29] master Q_DFF end
  gate ahb_slave.dst_addr[30] master Q_DFF end
  gate ahb_slave.dst_addr[1] master Q_DFF end
  gate ahb_slave.dst_addr[2] master Q_DFF end
  gate ahb_slave.dst_addr[3] master Q_DFF end
  gate ahb_slave.dst_addr[4] master Q_DFF end
  gate ahb_slave.dst_addr[5] master Q_DFF end
  gate ahb_slave.dst_addr[6] master Q_DFF end
  gate ahb_slave.dst_addr[7] master Q_DFF end
  gate ahb_slave.dst_addr[8] master Q_DFF end
  gate ahb_slave.dst_addr[9] master Q_DFF end
  gate ahb_slave.dst_addr[10] master Q_DFF end
  gate ahb_slave.dst_addr[11] master Q_DFF end
  gate ahb_slave.dst_addr[12] master Q_DFF end
  gate ahb_slave.dst_addr[13] master Q_DFF end
  gate ahb_slave.dst_addr[14] master Q_DFF end
  gate ahb_slave.dst_addr[15] master Q_DFF end
  gate ahb_slave.src_addr[18] master Q_DFF end
  gate ahb_slave.src_addr[19] master Q_DFF end
  gate ahb_slave.src_addr[20] master Q_DFF end
  gate ahb_slave.src_addr[21] master Q_DFF end
  gate ahb_slave.src_addr[22] master Q_DFF end
  gate ahb_slave.src_addr[23] master Q_DFF end
  gate ahb_slave.src_addr[24] master Q_DFF end
  gate ahb_sla