demo_amba.qdf

appnote65_quickmips_ahb_interface_design_example AHB接口设计

  gate ahb_slave.src_addr_0[10] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[11] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[11] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[12] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[12] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[13] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[13] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[14] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[14] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[15] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[15] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[16] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[16] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[17] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[17] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[18] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[18] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[19] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[19] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[20] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[20] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[21] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[21] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[22] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[22] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[23] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[23] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[24] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[24] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[25] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[25] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[26] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[26] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[27] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[27] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[28] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[28] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[29] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[29] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[30] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[30] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[31] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[31] master Q_MUX2X1 end
  gate ahb_slave.un1_un1_prevsel_3 master Q_AND2I1 end
  gate ahb_slave.un1_un1_un1_prevsel_2 master Q_OR2I0 end
  gate ahb_slave.G_247 master Q_AND2I1 end
  gate ahb_slave.dst_addr_0[0] master Q_MUX2X0 end
  gate ahb_slave.dst_addr_0[1] master Q_MUX2X0 end
  gate ahb_slave.dst_addr_11[2] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[2] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[3] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[3] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[4] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[4] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[5] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[5] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[6] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[6] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[7] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[7] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[8] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[8] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[9] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[9] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[10] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[10] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[11] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[11] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[12] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[12] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[13] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[13] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[14] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[14] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[15] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[15] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[16] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[16] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[17] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[17] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[18] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[18] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[19] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[19] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[20] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[20] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[21] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[21] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[22] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[22] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[23] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[23] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[24] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[24] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[25] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[25] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[26] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[26] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[27] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[27] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[28] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[28] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[29] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[29] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[30] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[30] master Q_MUX2X1 end
  gate ahb_slave.dst_addr_11[31] master Q_MUX2X3 end
  gate ahb_slave.dst_addr_0[31] master Q_MUX2X1 end
  gate ahb_slave.start_0 master Q_MUX2X0 end
  gate ahb_slave.int_en_0 master Q_MUX2X0 end
  gate ahb_slave.int_clr_0 master Q_MUX2X0 end
  gate ahb_slave.dma_en_0 master Q_MUX2X0 end
  gate ahb_slave.block_size_0[0] master Q_MUX2X0 end
  gate ahb_slave.block_size_0[1] master Q_MUX2X0 end
  gate ahb_slave.block_size_0[2] master Q_MUX2X0 end
  gate ahb_slave.block_size_0[3] master Q_MUX2X0 end
  gate ahb_slave.block_size_0[4] master Q_MUX2X0 end
  gate ahb_slave.un1_ahbs_hsel_0_and2_0_and2 master Q_AND3I1 end
  gate ahb_slave.G_258 master Q_AND2I0 end
  gate ahb_slave.sel_ctrl_0_and2_0_and2 master Q_AND2I1 end
  gate ahb_slave.next_state32_0_and2_0_and2 master Q_AND3I0 end
  gate appreq_sm.un1_nextstate49_i_0 master Q_OR2I1 end
  gate app_inst.done master Q_AND4I2 pack end
  gate appreq_sm.G_8 master Q_MUX2X3 end
  gate appreq_sm.N_6_i master Q_AND2I2 end
  gate busreq_sm.G_35 master Q_AND2I2 end
  gate busreq_sm.rd_req_0_and2 master Q_AND2I0 end
  gate busreq_sm.nextstate_i_i[0] master Q_OR3I0 end
  gate non_zero_104 master Q_AND2I2 end
  gate non_zero_109 master Q_AND4I3 end
  gate non_zero_100 master Q_AND2I2 end
  gate non_zero_98 master Q_AND2I2 end
  gate non_zero_107 master Q_AND4I2 pack end
  gate non_zero_105 master Q_AND2I2 end
  gate non_zero master Q_AND6I3 end
  gate busreq_sm.G_36 master Q_MUX2X0 end
  gate busreq_sm.nextstate_i_and2[1] master Q_AND2I1 end
  gate busreq_sm.N_29_i master Q_AND3I3 end
  gate busreq_sm.nextstate_and2_0_and2[2] master Q_AND3I0 end
  gate ahb_master.un1_haddr_prev18_1 master Q_AND2I0 end
  gate ahb_master.un4_req_done master Q_OR2I0 end
  gate busreq_sm.wr_req_0_and2 master Q_AND2I0 end
  gate ahb_master.haddr_reg_11_sn.G_8_0 master Q_OR2I1 end
  gate ahb_master.word_count_7[0] master Q_MUX2X0 end
  gate ahb_master.word_count_7[1] master Q_MUX2X0 end
  gate ahb_master.word_count_7[2] master Q_MUX2X0 end
  gate ahb_master.word_count_7[3] master Q_MUX2X0 end
  gate ahb_master.word_count_7[4] master Q_MUX2X0 end
  gate ahb_master.un1_hburst_o58_1 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o61_7_1 master Q_AND2I0 end
  gate ahb_master.lastbrstrd master Q_AND4I1 end
  gate ahb_master.hburst_o60 master Q_AND3I0 end
  gate ahb_master.un1_hburst_o60 master Q_AND2I0 end
  gate ahb_master.un1_un1_un1_un1_hburst_o_1 master Q_AND2I0 end
  gate ahb_master.un1_rddf_wren35_3 master Q_OR2I0 end
  gate ahb_master.un1_hburst_o61_3 master Q_AND2I1 end
  gate ahb_master.un1_un1_hburst_o61_2 master Q_OR3I0 end
  gate ahb_master.un184_ahm_busreq_reg_un184_ahm_busreq_reg master Q_AND2I2 end
  gate ahb_master.un188_ahm_busreq_reg master Q_AND2I1 end
  gate ahb_master.un1_un188_ahm_busreq_reg_2 master Q_AND2I0 end
  gate ahb_master.hburst_o34 master Q_AND2I0 end
  gate ahb_master.hburst_o59 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o59_1 master Q_AND2I0 end
  gate ahb_master.un1_hwrite_o_1 master Q_AND2I0 end
  gate ahb_master.un1_un1_hburst_o63 master Q_OR2I0 end
  gate ahb_master.un1_hburst_o61 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o66_1 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o67 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o62 master Q_AND2I0 end
  gate ahb_master.ahb_master_state_74_1_iv_0_159 master Q_OR4I0 end
  gate ahb_master.ahb_master_state_74_1_iv_0_162 master Q_OR4I0 end
  gate ahb_master.un1_rddf_wren35 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o67_2 master Q_AND2I0 end
  gate ahb_master.un1_un188_ahm_busreq_reg_3 master Q_AND2I0 end
  gate ahb_master.un1_un1_hburst_o61_1 master Q_OR3I0 end
  gate ahb_master.ahb_master_state_74_1_iv[0] master Q_OR4I0 end
  gate ahb_master.un1_rddf_wren35_2 master Q_OR2I0 end
  gate ahb_master.un1_rddf_wren36_i master Q_AND2I2 end
  gate ahb_master.un1_un188_ahm_busreq_reg_4 master Q_AND2I0 end
  gate ahb_master.ahb_master_state_0[0] master Q_MUX2X1 end
  gate ahb_master.lastbrstwr master Q_AND2I0 end
  gate ahb_master.un1_hburst_o66_4 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o66_2_1 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o63_1 master Q_AND2I0 end
  gate ahb_master.un1_ahm_busreq_reg43 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o67_6 master Q_AND2I0 end
  gate ahb_master.un1_un1_hburst_o66 master Q_OR4I0 end
  gate ahb_master.un1_un1_un1_un1_hburst_o master Q_AND2I0 end
  gate ahb_master.un1_hburst_o66_3 master Q_AND2I0 end
  gate ahb_master.ahb_master_state_74_1_iv_1_178 master Q_AND3I3 end
  gate ahb_master.un1_hburst_o61_5_1 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o61_5 master Q_AND2I0 end
  gate ahb_master.un1_un1_hburst_o61 master Q_OR2I0 end
  gate ahb_master.ahb_master_state_74_1_iv_1_179 master Q_AND2I1 end
  gate ahb_master.ahb_master_state_74_1_iv_1_180 master Q_OR2I1 end
  gate ahb_master.ahb_master_state_74_1_iv[1] master Q_AND3I3 end
  gate ahb_master.ahb_master_state_0[1] master Q_MUX2X1 end
  gate ahb_master.un1_hburst_o62_4 master Q_AND2I0 end
  gate ahb_master.un1_ahm_busreq_reg43_1 master Q_AND2I0 end
  gate ahb_master.un1_un1_hburst_o62_1 master Q_OR3I0 end
  gate ahb_master.ahb_master_state_74_1_iv[2] master Q_AND3I3 end
  gate ahb_master.ahb_master_state_0[2] master Q_MUX2X1 end
  gate ahb_master.ahb_master_state_74_1_iv_3_151 master Q_OR4I0 end
  gate ahb_master.ahb_master_state_74_1_iv[3] master Q_AND3I3 end
  gate ahb_master.ahb_master_state_0[3] master Q_MUX2X1 end
  gate ahb_master.un1_hburst_o58_3 master Q_OR2I1 end
  gate ahb_master.un1_un188_ahm_busreq_reg master Q_AND2I0 end
  gate ahb_master.un1_hburst_o66 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o62_3 master Q_AND2I0 end
  gate ahb_master.un1_rddf_wren35_1 master Q_AND2I1 end
  gate ahb_master.un1_rddf_wren56 master Q_AND2I2 end
  gate ahb_master.un1_hburst_o67_5 master Q_AND2I1 end
  gate ahb_master.un1_un1_hburst_o58 master Q_OR5I1 end
  gate ahb_master.un1_rddf_wren36_2 master Q_AND2I2 end
  gate ahb_master.un1_hburst_o66_5 master Q_AND2I1 end
  gate ahb_master.un1_hburst_o60_2 master Q_AND3I0 end
  gate ahb_master.un1_rddf_wren36_1 master Q_AND2I2 end
  gate ahb_master.un1_hburst_o67_4 master Q_AND2I1 end
  gate ahb_master.un1_un1_un1_hburst_o58_171 master Q_AND3I3 end
  gate ahb_master.un1_un188_ahm_busreq_reg_1 master Q_AND2I0 end
  gate ahb_master.un1_un1_un1_hburst_o58_172 master Q_AND2I1 end
  gate ahb_master.un1_rddf_wren35_4 master Q_AND2I0 end
  gate ahb_master.un1_rddf_wren36_3 master Q_AND2I2 end
  gate ahb_master.un1_hburst_o61_9 master Q_AND2I1 end
  gate ahb_master.un1_un1_un1_hburst_o58_173 master Q_OR2I1 end
  gate ahb_master.hburst_o13 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o34_1 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o13_1 master Q_AND2I0 end
  gate ahb_master.hburst_o26 master Q_AND2I0 end
  gate ahb_master.un1_hburst_o26_1 master Q_AND2I0 end
  gate ahb_master.un1_un1_hburst_o13_1 master Q_AND2I2 end
  gate ahb_master.un1_hburst_o59_2 master Q_AND2I1 end
  gate ahb_master.un1_un1_un1_hburst_o58 master Q_OR4I0 end
  gate ahb_master.hbusreq_o_0 master Q_MUX2X0 end
  gate ahb_master.rddf_wren_24 master Q_AND3I3 end
  gate ahb_master.un79_rddf_wren_un79_rddf_wren master Q_AND3I3 end
  gate ahb_master.un1_ahb_master_state_1 master Q_AND2I1 end
  gate ahb_master.un1_hburst_o61_4 master Q_AND2I0 end
  gate ahb_master.un1_un1_un85_rddf_wren master Q_OR5I1 end
  gate ahb_master.rddf_wren_0 master Q_MUX2X1 end
  gate ahb_master.un1_un1_hburst_o13 master Q_AND2I1 end
  gate ahb_master.un1_un1_hburst_o26 master Q_AND2I1 end
  gate ahb_master.un1_un1_un1_hburst_o13 master Q_AND2I2 end
  gate ahb_master.hburst_o_1_0[0] master Q_MUX2X2 end
  gate ahb_master.burstwrflag_last_n9 master Q_OR2I0 end
  gate ahb_master.burstwrflag_last_n_0 master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[0] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[1] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[2] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[3] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[4] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[5] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[6] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[7] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[8] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[9] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[10] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[11] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[12] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[13] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[14] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[15] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[16] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[17] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[18] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[19] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[20] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[21] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[22] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[23] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[24] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[25] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[26] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[27] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[28] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[29] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[30] master Q_MUX2X0 end
  gate ahb_master.hwdata_o_0[31] master Q_MUX2X0 end
  gate ahb_master.hwrite_o_6_0 master Q_OR2I0 end
  gate ahb_master.hwrite_o_0 master Q_MUX2X0 end
  gate ahb_master.latch_addr_0 master Q_MUX2X0 end
  gate ahb_master.haddr_reg_11_0[29] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[29] master Q_MUX2X1 end
  gate ahb_master.haddr_reg_11_0[28] master Q_MUX2X3 end
  gate ahb_master.haddr_reg_11[28] master Q_MUX2X1 end