demo_amba.qdf

appnote65_quickmips_ahb_interface_design_example AHB接口设计

  gate ahb_slave.G_138_1.CO4 master Q_AND2 end
  gate ahb_slave.G_138_1.CO5 master Q_AND2 end
  gate ahb_slave.G_138_1.CO7 master Q_AND2 end
  gate ahb_slave.G_138_1.CO8 master Q_AND2 end
  gate ahb_slave.G_138_1.CO10 master Q_AND2 end
  gate ahb_slave.G_138_1.CO11 master Q_AND2 end
  gate ahb_slave.G_138_1.CO13 master Q_AND2 end
  gate ahb_slave.G_138_1.CO14 master Q_AND2 end
  gate ahb_slave.G_138_1.CO16 master Q_AND2 end
  gate ahb_slave.G_138_1.CO17 master Q_AND2 end
  gate ahb_slave.G_138_1.CO19 master Q_AND2 end
  gate ahb_slave.G_138_1.CO20 master Q_AND2 end
  gate ahb_slave.G_138_1.CO22 master Q_AND2 end
  gate ahb_slave.G_138_1.CO23 master Q_AND2 end
  gate ahb_slave.G_138_1.SUM0 master Q_INCX end
  gate ahb_slave.G_138_1.SUM1 master Q_INCX end
  gate ahb_slave.G_138_1.SUM2 master Q_INCX end
  gate ahb_slave.G_138_1.SUM3 master Q_INCX end
  gate ahb_slave.G_138_1.SUM4 master Q_INCX end
  gate ahb_slave.G_138_1.SUM5 master Q_INCX end
  gate ahb_slave.G_138_1.SUM6 master Q_INCX end
  gate ahb_slave.G_138_1.SUM7 master Q_INCX end
  gate ahb_slave.G_138_1.SUM8 master Q_INCX end
  gate ahb_slave.G_138_1.SUM9 master Q_INCX end
  gate ahb_slave.G_138_1.SUM10 master Q_INCX end
  gate ahb_slave.G_138_1.SUM11 master Q_INCX end
  gate ahb_slave.G_138_1.SUM12 master Q_INCX end
  gate ahb_slave.G_138_1.SUM13 master Q_INCX end
  gate ahb_slave.G_138_1.SUM14 master Q_INCX end
  gate ahb_slave.G_138_1.SUM15 master Q_INCX end
  gate ahb_slave.G_138_1.SUM16 master Q_INCX end
  gate ahb_slave.G_138_1.SUM17 master Q_INCX end
  gate ahb_slave.G_138_1.SUM18 master Q_INCX end
  gate ahb_slave.G_138_1.SUM19 master Q_INCX end
  gate ahb_slave.G_138_1.SUM20 master Q_INCX end
  gate ahb_slave.G_138_1.SUM21 master Q_INCX end
  gate ahb_slave.G_138_1.SUM22 master Q_INCX end
  gate ahb_slave.G_138_1.SUM23 master Q_INCX end
  gate ahb_slave.G_138_1.SUM24 master Q_INCX end
  gate ahb_slave.G_131.I_2 master LOGIC2 end
  gate ahb_slave.G_131.I_7 master LOGIC2 end
  gate ahb_slave.G_131.I_12 master LOGIC2 end
  gate ahb_slave.G_131.I_17 master LOGIC2 end
  gate ahb_slave.G_131.I_22 master LOGIC2 end
  gate ahb_slave.G_131.I_27 master LOGIC2 end
  gate ahb_slave.G_131.I_32 master LOGIC2 end
  gate ahb_slave.G_131.I_37 master LOGIC2 end
  gate ahb_slave.G_131.I_42 master LOGIC2 end
  gate ahb_slave.G_131.I_47 master LOGIC2 end
  gate ahb_slave.G_131.I_52 master LOGIC2 end
  gate ahb_slave.G_131.I_57 master LOGIC2 end
  gate ahb_slave.G_131.I_62 master LOGIC2 end
  gate ahb_master.un1_word_count_1.CO2 master Q_DECSKIP pack end
  gate ahb_master.I_37 master Q_DECX end
  gate ahb_master.I_38 master Q_DECX end
  gate ahb_master.I_39 master Q_DECX end
  gate ahb_master.I_40 master Q_DECX end
  gate ahb_master.I_41 master Q_DECX end
  gate ahb_master.un1_haddr_reg_1.CO6 master Q_INCSKIP2 pack end
  gate ahb_master.un1_haddr_reg_1.CO12 master Q_INCSKIP2 pack end
  gate ahb_master.un1_haddr_reg_1.CO18 master Q_INCSKIP2 pack end
  gate ahb_master.un1_haddr_reg_1.CO24 master Q_INCSKIP2 pack end
  gate ahb_master.un1_haddr_reg_1.CO27 master Q_INCSKIP pack end
  gate ahb_master.un1_haddr_reg_1.CO1 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO2 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO4 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO5 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO7 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO8 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO10 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO11 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO13 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO14 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO16 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO17 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO19 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO20 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO22 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO23 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO25 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO26 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.CO28 master Q_AND2 end
  gate ahb_master.un1_haddr_reg_1.SUM0 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM1 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM2 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM3 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM4 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM5 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM6 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM7 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM8 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM9 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM10 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM11 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM12 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM13 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM14 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM15 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM16 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM17 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM18 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM19 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM20 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM21 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM22 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM23 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM24 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM25 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM26 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM27 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM28 master Q_INCX end
  gate ahb_master.un1_haddr_reg_1.SUM29 master Q_INCX end
  gate ahb_master.htrans_o_sn.htrans_o_17.htrans_o_2 master Q_AND2I0 end
  gate ahb_master.htrans_o_2[0] master Q_MUX2X0 end
  gate ahb_master.htrans_o_sn.htrans_o_17.htrans_o_7 master Q_XOR2I0 end
  gate ahb_master.htrans_o_sn.htrans_o_17.htrans_o_9 master Q_MUX2X0 end
  gate ahb_master.htrans_o[0] master Q_AND2I0 end
  gate ahb_master.htrans_o_2[1] master Q_OR2I1 end
  gate ahb_master.htrans_o[1] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[0] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata_sn.G_11 master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_0[0] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_2[0] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata_sn.G_18 master Q_XOR2I0 end
  gate ahb_slave.ahbs_hrdata_sn.G_9_0_and2 master Q_AND2I1 end
  gate ahb_slave.ahbs_hrdata[0] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[1] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata_0[1] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_2[1] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[1] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[2] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata_0[2] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_2[2] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[2] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[3] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata_0[3] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_2[3] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[3] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[4] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[4] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[5] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[5] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[6] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[6] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[7] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[7] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[8] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[8] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[9] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[9] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[10] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[10] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[11] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[11] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[12] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[12] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[13] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[13] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[14] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[14] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[15] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[15] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[16] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[16] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[17] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[17] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[18] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[18] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[19] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[19] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[20] master Q_MUX2X3 end
  gate ahb_slave.ahbs_hrdata[20] master Q_MUX2X2 end
  gate ahb_slave.ahbs_hrdata_1[21] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[21] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[22] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[22] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[23] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[23] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[24] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[24] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[25] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[25] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[26] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[26] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[27] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[27] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[28] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[28] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[29] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[29] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[30] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[30] master Q_AND2I0 end
  gate ahb_slave.ahbs_hrdata_1[31] master Q_MUX2X0 end
  gate ahb_slave.ahbs_hrdata[31] master Q_AND2I0 end
  gate app_inst.done_2 master Q_AND2I2 end
  gate app_inst.un1_push master Q_AND4I3 end
  gate app_inst.push_1 master Q_AND2I2 end
  gate app_inst.un1_wait_count_94 master Q_AND2I2 end
  gate app_inst.un1_wait_count_92 master Q_AND2I2 end
  gate app_inst.un1_wait_count master Q_OR6I2 end
  gate app_inst.un1_un1_wait_count master Q_AND2I0 end
  gate app_inst.wait_flag_6 master Q_OR2I0 end
  gate app_inst.word_count_6[0] master Q_MUX2X0 end
  gate app_inst.word_count_6[1] master Q_MUX2X0 end
  gate app_inst.word_count_6[2] master Q_MUX2X0 end
  gate app_inst.word_count_6[3] master Q_MUX2X0 end
  gate app_inst.word_count_6[4] master Q_MUX2X0 end
  gate app_inst.wait_count_6[3] master Q_MUX2X0 end
  gate app_inst.wait_count_6[4] master Q_MUX2X0 end
  gate app_inst.wait_count_6[5] master Q_MUX2X0 end
  gate app_inst.wait_count_6[6] master Q_MUX2X0 end
  gate app_inst.wait_count_6[7] master Q_MUX2X0 end
  gate out_fifo.un1_empty_0.N_126_i master Q_XOR2I0 end
  gate out_fifo.un1_empty_0.I_91 master Q_XOR2I0 end
  gate out_fifo.un1_empty_0.I_25_117 master Q_AND2I2 end
  gate out_fifo.un1_empty_0.N_158_i master Q_XNOR2I0 end
  gate out_fifo.un1_empty_0.N_93_i master Q_XNOR2I0 end
  gate out_fifo.un1_empty_0.N_60_i master Q_XOR2I0 end
  gate out_fifo.un1_empty_0.I_125 master Q_XOR2I0 end
  gate out_fifo.un1_empty_0.I_160 master Q_XOR2I0 end
  gate out_fifo.un1_empty_0.I_25 master Q_AND6I3 end
  gate out_fifo.empty master Q_AND2I1 end
  gate ahb_master.hburst_o66_1 master Q_AND2I0 end
  gate ahb_master.hburst_o66 master Q_AND2I0 end
  gate ahb_master.haddr_prev18_2 master Q_OR2I0 end
  gate ahb_master.pop master Q_AND3I0 end
  gate out_fifo.un1_last_op13 master Q_MUX2X0 end
  gate out_fifo.last_op_0 master Q_MUX2X0 end
  gate in_fifo.un1_empty_0.N_126_i master Q_XOR2I0 end
  gate in_fifo.un1_empty_0.I_91 master Q_XOR2I0 end
  gate in_fifo.un1_empty_0.I_25_122 master Q_AND2I2 end
  gate in_fifo.un1_empty_0.N_158_i master Q_XNOR2I0 end
  gate in_fifo.un1_empty_0.N_93_i master Q_XNOR2I0 end
  gate in_fifo.un1_empty_0.N_60_i master Q_XOR2I0 end
  gate in_fifo.un1_empty_0.I_125 master Q_XOR2I0 end
  gate in_fifo.un1_empty_0.I_160 master Q_XOR2I0 end
  gate in_fifo.un1_empty_0.I_25 master Q_AND6I3 end
  gate in_fifo.empty master Q_AND2I1 end
  gate ahb_master.rddf_wren35 master Q_AND2I0 end
  gate ahb_master.push master Q_AND2I0 end
  gate in_fifo.un1_last_op13 master Q_OR2I0 end
  gate in_fifo.last_op_0 master Q_MUX2X0 end
  gate in_fifo.full master Q_AND2I0 end
  gate out_fifo.full master Q_AND2I0 end
  gate ahb_slave.un1_prevsel master Q_AND2I0 end
  gate busreq_sm.rd_update_0_and2 master Q_AND2I0 end
  gate ahb_slave.un1_un1_prevsel_1 master Q_AND3I0 end
  gate ahb_slave.block_count_11[0] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[1] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[2] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[3] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[4] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[5] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[6] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[7] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[8] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[9] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[10] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[11] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[12] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[13] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[14] master Q_MUX2X0 end
  gate ahb_slave.block_count_11[15] master Q_MUX2X0 end
  gate ahb_slave.un1_un1_prevsel_4 master Q_AND2I1 end
  gate ahb_slave.un1_un1_un1_un1_prevsel master Q_OR2I0 end
  gate ahb_slave.G_249 master Q_AND2I1 end
  gate ahb_slave.src_addr_0[0] master Q_MUX2X0 end
  gate ahb_slave.src_addr_0[1] master Q_MUX2X0 end
  gate ahb_slave.src_addr_11[2] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[2] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[3] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[3] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[4] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[4] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[5] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[5] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[6] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[6] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[7] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[7] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[8] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[8] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[9] master Q_MUX2X3 end
  gate ahb_slave.src_addr_0[9] master Q_MUX2X1 end
  gate ahb_slave.src_addr_11[10] master Q_MUX2X3 end