demo_amba.qdf

appnote65_quickmips_ahb_interface_design_example AHB接口设计

   term QC port QC end
   term QR port QR end
   term QS port QS end
   term AZ port AZ end
   term FZ port FZ end
   term NZ port NZ end
   term OZ port OZ end
   term QZ port QZ end
   term VCC end
   term GND end
 end
 gate Q_INCSKIP2 cell LOGIC
   term CI port E1 end
   term A0 port F1 end
   term A1 port F3 end
   term A2 port F5 end
   term CO3 port NZ end
   term A3 port A1 end
   term A4 port A3 end
   term A5 port A5 end
   term CO6 port OZ end
   term VCC end
   term GND port F6 port F4 port F2 port E2 port D2 port D1 port C2 port C1 port B2 port B1 port A6 port A4 port A2 end
 end
 gate Q_INCX cell LOGIC
   term A port E2 port D1 end
   term E1 port F1 end
   term E2 port F3 end
   term E3 port F5 end
   term NE4 port F2 end
   term NE5 port F4 end
   term S port NZ end
   term VCC port E1 end
   term GND port F6 port D2 port C2 port C1 port B2 port B1 port A6 port A5 port A4 port A3 port A2 port A1 end
 end
 gate Q_AND2 cell LOGIC
   term A port A1 end
   term B port A3 end
   term Q port AZ end
   term VCC port A5 end
   term GND port A6 port A4 port A2 end
 end
 gate Q_INCSKIP cell LOGIC
   term CI port E1 end
   term A0 port F1 end
   term A1 port F3 end
   term A2 port F5 end
   term CO port NZ end
   term VCC port C1 port B1 end
   term GND port F6 port F4 port F2 port E2 port D2 port D1 port C2 port B2 port A6 port A5 port A4 port A3 port A2 port A1 end
 end
 gate Q_DECSKIP2 cell LOGIC
   term CI port E1 end
   term A0 port F2 end
   term A1 port F4 end
   term A2 port F6 end
   term CO3 port NZ end
   term A3 port A2 end
   term A4 port A4 end
   term A5 port A6 end
   term CO6 port OZ end
   term VCC port F5 port F3 port F1 port D1 port C1 port B1 port A5 port A3 port A1 end
   term GND port E2 port D2 port C2 port B2 end
 end
 gate Q_DECX cell LOGIC
   term A port E2 port D1 end
   term E1 port F2 end
   term E2 port F4 end
   term E3 port F6 end
   term NE4 port F1 end
   term NE5 port F3 end
   term S port NZ end
   term VCC port F5 port E1 end
   term GND port D2 port C2 port C1 port B2 port B1 port A6 port A5 port A4 port A3 port A2 port A1 end
 end
 gate Q_DECSKIP cell LOGIC
   term CI port E1 end
   term A0 port F2 end
   term A1 port F4 end
   term A2 port F6 end
   term CO port NZ end
   term VCC port F5 port F3 port F1 port D1 port C1 port B1 end
   term GND port E2 port D2 port C2 port B2 port A6 port A5 port A4 port A3 port A2 port A1 end
 end
 gate xor2i0 cell LOGIC
   term A port F1 end
   term B port E2 port D1 end
   term Q port NZ end
   term VCC port A1 port A3 port A5 port B1 port C1 port E1 port F3 port F5 end
   term GND port A2 port A4 port A6 port B2 port C2 port D2 port F2 port F4 port F6 end
 end
 gate gclkbuff_25um cell HSCKMUX
   term A port IC end
   term Z port IZ end
   term VCC port IS end
 end
end
logical QDIF
  gates 1350
  nets 1929
  # instances
  gate QuickMIPScore master qmipsesp end
  gate hreset_ghreset master gclkbuff_25um end
  gate app_inst.xor2_1.xor_0 master xor2i0 end
  gate app_inst.xor2_1.xor_1 master xor2i0 end
  gate app_inst.xor2_1.xor_2 master xor2i0 end
  gate app_inst.xor2_1.xor_3 master xor2i0 end
  gate app_inst.xor2_1.xor_4 master xor2i0 end
  gate app_inst.xor2_1.xor_5 master xor2i0 end
  gate app_inst.xor2_1.xor_6 master xor2i0 end
  gate app_inst.xor2_1.xor_7 master xor2i0 end
  gate app_inst.xor2_1.xor_8 master xor2i0 end
  gate app_inst.xor2_1.xor_9 master xor2i0 end
  gate app_inst.xor2_1.xor_10 master xor2i0 end
  gate app_inst.xor2_1.xor_11 master xor2i0 end
  gate app_inst.xor2_1.xor_12 master xor2i0 end
  gate app_inst.xor2_1.xor_13 master xor2i0 end
  gate app_inst.xor2_1.xor_14 master xor2i0 end
  gate app_inst.xor2_1.xor_15 master xor2i0 end
  gate app_inst.xor2_1.xor_16 master xor2i0 end
  gate app_inst.xor2_1.xor_17 master xor2i0 end
  gate app_inst.xor2_1.xor_18 master xor2i0 end
  gate app_inst.xor2_1.xor_19 master xor2i0 end
  gate app_inst.xor2_1.xor_20 master xor2i0 end
  gate app_inst.xor2_1.xor_21 master xor2i0 end
  gate app_inst.xor2_1.xor_22 master xor2i0 end
  gate app_inst.xor2_1.xor_23 master xor2i0 end
  gate app_inst.xor2_1.xor_24 master xor2i0 end
  gate app_inst.xor2_1.xor_25 master xor2i0 end
  gate app_inst.xor2_1.xor_26 master xor2i0 end
  gate app_inst.xor2_1.xor_27 master xor2i0 end
  gate app_inst.xor2_1.xor_28 master xor2i0 end
  gate app_inst.xor2_1.xor_29 master xor2i0 end
  gate app_inst.xor2_1.xor_30 master xor2i0 end
  gate app_inst.xor2_1.xor_31 master xor2i0 end
  gate out_fifo.m.r128a32_25umI1 master RAM128X18_25UM end
  gate out_fifo.m.r128a32_25umI2 master RAM128X18_25UM end
  gate in_fifo.m.r128a32_25umI1 master RAM128X18_25UM end
  gate in_fifo.m.r128a32_25umI2 master RAM128X18_25UM end
  gate app_inst.un1_word_count_1.CO2 master Q_DECSKIP pack end
  gate I_2 master Q_DECX end
  gate I_3 master Q_DECX end
  gate I_4 master Q_DECX end
  gate I_5 master Q_DECX end
  gate I_6 master Q_DECX end
  gate app_inst.un1_wait_count_1.CO5 master Q_DECSKIP2 pack end
  gate I_7 master Q_DECX end
  gate I_8 master Q_DECX end
  gate I_9 master Q_DECX end
  gate I_10 master Q_DECX end
  gate I_11 master Q_DECX end
  gate I_12 master Q_DECX end
  gate I_13 master Q_DECX end
  gate I_14 master Q_DECX end
  gate out_fifo.wptr_5_1.CO3 master Q_INCSKIP pack end
  gate out_fifo.wptr_5_1.CO1 master Q_AND2 end
  gate out_fifo.wptr_5_1.CO2 master Q_AND2 end
  gate out_fifo.wptr_5_1.CO4 master Q_AND2 end
  gate out_fifo.wptr_5_1.CO5 master Q_AND2 end
  gate out_fifo.wptr_5_1.SUM0 master Q_INCX end
  gate out_fifo.wptr_5_1.SUM1 master Q_INCX end
  gate out_fifo.wptr_5_1.SUM2 master Q_INCX end
  gate out_fifo.wptr_5_1.SUM3 master Q_INCX end
  gate out_fifo.wptr_5_1.SUM4 master Q_INCX end
  gate out_fifo.wptr_5_1.SUM5 master Q_INCX end
  gate out_fifo.wptr_5_1.SUM6 master Q_INCX end
  gate out_fifo.rptr_5_1.CO3 master Q_INCSKIP pack end
  gate out_fifo.rptr_5_1.CO1 master Q_AND2 end
  gate out_fifo.rptr_5_1.CO2 master Q_AND2 end
  gate out_fifo.rptr_5_1.CO4 master Q_AND2 end
  gate out_fifo.rptr_5_1.CO5 master Q_AND2 end
  gate out_fifo.rptr_5_1.SUM0 master Q_INCX end
  gate out_fifo.rptr_5_1.SUM1 master Q_INCX end
  gate out_fifo.rptr_5_1.SUM2 master Q_INCX end
  gate out_fifo.rptr_5_1.SUM3 master Q_INCX end
  gate out_fifo.rptr_5_1.SUM4 master Q_INCX end
  gate out_fifo.rptr_5_1.SUM5 master Q_INCX end
  gate out_fifo.rptr_5_1.SUM6 master Q_INCX end
  gate in_fifo.wptr_5_1.CO3 master Q_INCSKIP pack end
  gate in_fifo.wptr_5_1.CO1 master Q_AND2 end
  gate in_fifo.wptr_5_1.CO2 master Q_AND2 end
  gate in_fifo.wptr_5_1.CO4 master Q_AND2 end
  gate in_fifo.wptr_5_1.CO5 master Q_AND2 end
  gate in_fifo.wptr_5_1.SUM0 master Q_INCX end
  gate in_fifo.wptr_5_1.SUM1 master Q_INCX end
  gate in_fifo.wptr_5_1.SUM2 master Q_INCX end
  gate in_fifo.wptr_5_1.SUM3 master Q_INCX end
  gate in_fifo.wptr_5_1.SUM4 master Q_INCX end
  gate in_fifo.wptr_5_1.SUM5 master Q_INCX end
  gate in_fifo.wptr_5_1.SUM6 master Q_INCX end
  gate in_fifo.rptr_5_1.CO3 master Q_INCSKIP pack end
  gate in_fifo.rptr_5_1.CO1 master Q_AND2 end
  gate in_fifo.rptr_5_1.CO2 master Q_AND2 end
  gate in_fifo.rptr_5_1.CO4 master Q_AND2 end
  gate in_fifo.rptr_5_1.CO5 master Q_AND2 end
  gate in_fifo.rptr_5_1.SUM0 master Q_INCX end
  gate in_fifo.rptr_5_1.SUM1 master Q_INCX end
  gate in_fifo.rptr_5_1.SUM2 master Q_INCX end
  gate in_fifo.rptr_5_1.SUM3 master Q_INCX end
  gate in_fifo.rptr_5_1.SUM4 master Q_INCX end
  gate in_fifo.rptr_5_1.SUM5 master Q_INCX end
  gate in_fifo.rptr_5_1.SUM6 master Q_INCX end
  gate ahb_slave.un1_block_count.CO5 master Q_DECSKIP2 pack end
  gate ahb_slave.un1_block_count.CO11 master Q_DECSKIP2 pack end
  gate ahb_slave.un1_block_count.CO14 master Q_DECSKIP pack end
  gate ahb_slave.I_230 master Q_DECX end
  gate ahb_slave.I_231 master Q_DECX end
  gate ahb_slave.I_232 master Q_DECX end
  gate ahb_slave.I_233 master Q_DECX end
  gate ahb_slave.I_234 master Q_DECX end
  gate ahb_slave.I_235 master Q_DECX end
  gate ahb_slave.I_236 master Q_DECX end
  gate ahb_slave.I_237 master Q_DECX end
  gate ahb_slave.I_238 master Q_DECX end
  gate ahb_slave.I_239 master Q_DECX end
  gate ahb_slave.I_240 master Q_DECX end
  gate ahb_slave.I_241 master Q_DECX end
  gate ahb_slave.I_242 master Q_DECX end
  gate ahb_slave.I_243 master Q_DECX end
  gate ahb_slave.I_244 master Q_DECX end
  gate ahb_slave.I_245 master Q_DECX end
  gate ahb_slave.G_171_1.CO6 master Q_INCSKIP2 pack end
  gate ahb_slave.G_171_1.CO12 master Q_INCSKIP2 pack end
  gate ahb_slave.G_171_1.CO18 master Q_INCSKIP2 pack end
  gate ahb_slave.G_171_1.CO21 master Q_INCSKIP pack end
  gate ahb_slave.G_171_1.CO1 master Q_AND2 end
  gate ahb_slave.G_171_1.CO2 master Q_AND2 end
  gate ahb_slave.G_171_1.CO4 master Q_AND2 end
  gate ahb_slave.G_171_1.CO5 master Q_AND2 end
  gate ahb_slave.G_171_1.CO7 master Q_AND2 end
  gate ahb_slave.G_171_1.CO8 master Q_AND2 end
  gate ahb_slave.G_171_1.CO10 master Q_AND2 end
  gate ahb_slave.G_171_1.CO11 master Q_AND2 end
  gate ahb_slave.G_171_1.CO13 master Q_AND2 end
  gate ahb_slave.G_171_1.CO14 master Q_AND2 end
  gate ahb_slave.G_171_1.CO16 master Q_AND2 end
  gate ahb_slave.G_171_1.CO17 master Q_AND2 end
  gate ahb_slave.G_171_1.CO19 master Q_AND2 end
  gate ahb_slave.G_171_1.CO20 master Q_AND2 end
  gate ahb_slave.G_171_1.CO22 master Q_AND2 end
  gate ahb_slave.G_171_1.CO23 master Q_AND2 end
  gate ahb_slave.G_171_1.SUM0 master Q_INCX end
  gate ahb_slave.G_171_1.SUM1 master Q_INCX end
  gate ahb_slave.G_171_1.SUM2 master Q_INCX end
  gate ahb_slave.G_171_1.SUM3 master Q_INCX end
  gate ahb_slave.G_171_1.SUM4 master Q_INCX end
  gate ahb_slave.G_171_1.SUM5 master Q_INCX end
  gate ahb_slave.G_171_1.SUM6 master Q_INCX end
  gate ahb_slave.G_171_1.SUM7 master Q_INCX end
  gate ahb_slave.G_171_1.SUM8 master Q_INCX end
  gate ahb_slave.G_171_1.SUM9 master Q_INCX end
  gate ahb_slave.G_171_1.SUM10 master Q_INCX end
  gate ahb_slave.G_171_1.SUM11 master Q_INCX end
  gate ahb_slave.G_171_1.SUM12 master Q_INCX end
  gate ahb_slave.G_171_1.SUM13 master Q_INCX end
  gate ahb_slave.G_171_1.SUM14 master Q_INCX end
  gate ahb_slave.G_171_1.SUM15 master Q_INCX end
  gate ahb_slave.G_171_1.SUM16 master Q_INCX end
  gate ahb_slave.G_171_1.SUM17 master Q_INCX end
  gate ahb_slave.G_171_1.SUM18 master Q_INCX end
  gate ahb_slave.G_171_1.SUM19 master Q_INCX end
  gate ahb_slave.G_171_1.SUM20 master Q_INCX end
  gate ahb_slave.G_171_1.SUM21 master Q_INCX end
  gate ahb_slave.G_171_1.SUM22 master Q_INCX end
  gate ahb_slave.G_171_1.SUM23 master Q_INCX end
  gate ahb_slave.G_171_1.SUM24 master Q_INCX end
  gate ahb_slave.G_164.I_2 master LOGIC2 end
  gate ahb_slave.G_164.I_7 master LOGIC2 end
  gate ahb_slave.G_164.I_12 master LOGIC2 end
  gate ahb_slave.G_164.I_17 master LOGIC2 end
  gate ahb_slave.G_164.I_22 master LOGIC2 end
  gate ahb_slave.G_164.I_27 master LOGIC2 end
  gate ahb_slave.G_164.I_32 master LOGIC2 end
  gate ahb_slave.G_164.I_37 master LOGIC2 end
  gate ahb_slave.G_164.I_42 master LOGIC2 end
  gate ahb_slave.G_164.I_47 master LOGIC2 end
  gate ahb_slave.G_164.I_52 master LOGIC2 end
  gate ahb_slave.G_164.I_57 master LOGIC2 end
  gate ahb_slave.G_164.I_62 master LOGIC2 end
  gate ahb_slave.G_138_1.CO6 master Q_INCSKIP2 pack end
  gate ahb_slave.G_138_1.CO12 master Q_INCSKIP2 pack end
  gate ahb_slave.G_138_1.CO18 master Q_INCSKIP2 pack end
  gate ahb_slave.G_138_1.CO21 master Q_INCSKIP pack end
  gate ahb_slave.G_138_1.CO1 master Q_AND2 end
  gate ahb_slave.G_138_1.CO2 master Q_AND2 end