demo_amba.qdf

appnote65_quickmips_ahb_interface_design_example AHB接口设计

#
# Synplify QuickLogic Technology Mapper, version 7.0.0, Build 129R
# Copyright (C) 1994-1995, Synplicity Inc.  All Rights Reserved
#
# File written on: Fri Sep 13 17:34:23 2002
QDIF 3
file ql901m
package ps680
tools
  design 3000
  logic optimizer 0
    option IgnorePack boolean false
  delay modeler 0
    option SpeedGrade string 4
end
library QDIF
 gates 40
 terms 282
 ports 1023
 gate Q_INPAD_25UM cell BIDIR
   term P port IP end
   term Q port IZ end
   term VCC port OSEL port OQI port ESEL end
   term GND port IQR port IQE port IQC port IE port EQE end
 end
 gate Q_OUTPAD_25UM cell BIDIR
   term A port OQI end
   term P port IP end
   term VCC port OSEL port IE port ESEL end
   term GND port IQR port IQE port IQC port EQE end
 end
 gate Q_IOPAD_25UM cell BIDIR
   term P port IP end
   term Q port IZ end
   term E port IE end
   term D port OQI end
   term VCC port OSEL port ESEL end
   term GND port IQR port IQE port IQC port EQE end
 end
 gate Q_DFF cell LOGIC
   term QC port QC end
   term QD port E1 end
   term QR port QR end
   term QS port QS end
   term QZ port QZ end
   term VCC port F5 port F3 port F1 port D2 port C2 port B2 port A5 port A3 port A1 end
   term GND port F6 port F4 port F2 port E2 port D1 port C1 port B1 port A6 port A4 port A2 end
 end
 gate Q_INV cell LOGIC
   term A port A6 end
   term Q port AZ end
   term VCC port A5 port A3 port A1 end
   term GND port A4 port A2 end
 end
 gate Q_OR3I1 cell LOGIC
   term A port F2 end
   term B port F4 end
   term C port F5 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port E2 port D1 port C1 port B1 port F3 port F1 end
   term GND port A6 port A4 port A2 port E1 port D2 port C2 port B2 port F6 end
 end
 gate Q_OR2I2 cell LOGIC
   term A port F1 end
   term B port F3 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port E2 port D1 port C1 port B1 port F5 end
   term GND port A6 port A4 port A2 port E1 port D2 port C2 port B2 port F6 port F4 port F2 end
 end
 gate Q_AND3I2 cell LOGIC
   term A port A1 end
   term B port A4 end
   term C port A6 end
   term Q port AZ end
   term VCC port A5 port A3 end
   term GND port A2 end
 end
 gate Q_OR5I1 cell LOGIC
   term A port F2 end
   term B port F4 end
   term C port F6 end
   term D port E1 end
   term E port F5 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port D1 port C1 port B1 port F3 port F1 end
   term GND port A6 port A4 port A2 port E2 port D2 port C2 port B2 end
 end
 gate Q_OR4I0 cell LOGIC
   term A port F2 end
   term B port F4 end
   term C port F6 end
   term D port E1 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port D1 port C1 port B1 port F5 port F3 port F1 end
   term GND port A6 port A4 port A2 port E2 port D2 port C2 port B2 end
 end
 gate Q_AND4I1 cell LOGIC
   term A port A1 end
   term B port A3 end
   term C port A5 end
   term D port A6 end
   term Q port AZ end
   term VCC end
   term GND port A4 port A2 end
 end
 gate Q_AND3I3 cell LOGIC
   term A port A2 end
   term B port A4 end
   term C port A6 end
   term Q port AZ end
   term VCC port A5 port A3 port A1 end
   term GND end
 end
 gate Q_OR3I0 cell LOGIC
   term A port F2 end
   term B port F4 end
   term C port F6 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port E2 port D1 port C1 port B1 port F5 port F3 port F1 end
   term GND port A6 port A4 port A2 port E1 port D2 port C2 port B2 end
 end
 gate Q_AND4I2 cell LOGIC
   term A port A1 end
   term B port A3 end
   term C port A6 end
   term D port A4 end
   term Q port AZ end
   term VCC port A5 end
   term GND port A2 end
 end
 gate Q_AND3I1 cell LOGIC
   term A port A1 end
   term B port A3 end
   term C port A6 end
   term Q port AZ end
   term VCC port A5 end
   term GND port A4 port A2 end
 end
 gate Q_MUX2X1 cell LOGIC
   term A port D2 end
   term B port E1 end
   term S port F1 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port D1 port C1 port B1 port F5 port F3 end
   term GND port A6 port A4 port A2 port E2 port C2 port B2 port F6 port F4 port F2 end
 end
 gate Q_AND3I0 cell LOGIC
   term A port A1 end
   term B port A3 end
   term C port A5 end
   term Q port AZ end
   term VCC end
   term GND port A6 port A4 port A2 end
 end
 gate Q_AND6I3 cell LOGIC
   term A port A1 end
   term B port A3 end
   term C port A5 end
   term D port A2 end
   term E port A4 end
   term F port A6 end
   term Q port AZ end
   term VCC end
   term GND end
 end
 gate Q_XNOR2I0 cell LOGIC
   term A port F1 end
   term B port E1 port D2 end
   term Q port NZ end
   term VCC port F5 port F3 port D1 port C1 port B1 port A5 port A3 port A1 end
   term GND port F6 port F4 port F2 port E2 port C2 port B2 port A6 port A4 port A2 end
 end
 gate Q_OR2I0 cell LOGIC
   term A port F2 end
   term B port F4 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port E2 port D1 port C1 port B1 port F5 port F3 port F1 end
   term GND port A6 port A4 port A2 port E1 port D2 port C2 port B2 port F6 end
 end
 gate Q_OR6I2 cell LOGIC
   term A port F2 end
   term B port F4 end
   term C port F6 end
   term D port E1 end
   term E port F3 end
   term F port F5 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port D1 port C1 port B1 port F1 end
   term GND port A6 port A4 port A2 port E2 port D2 port C2 port B2 end
 end
 gate Q_AND4I3 cell LOGIC
   term A port A1 end
   term B port A4 end
   term C port A6 end
   term D port A2 end
   term Q port AZ end
   term VCC port A5 port A3 end
   term GND end
 end
 gate Q_AND2I2 cell LOGIC
   term A port A4 end
   term B port A6 end
   term Q port AZ end
   term VCC port A5 port A3 port A1 end
   term GND port A2 end
 end
 gate Q_MUX2X2 cell LOGIC
   term A port D1 end
   term B port E2 end
   term S port F1 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port E1 port C1 port B1 port F5 port F3 end
   term GND port A6 port A4 port A2 port D2 port C2 port B2 port F6 port F4 port F2 end
 end
 gate Q_AND2I1 cell LOGIC
   term A port A1 end
   term B port A6 end
   term Q port AZ end
   term VCC port A5 port A3 end
   term GND port A4 port A2 end
 end
 gate Q_MUX2X3 cell LOGIC
   term A port D2 end
   term B port E2 end
   term S port F1 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port E1 port D1 port C1 port B1 port F5 port F3 end
   term GND port A6 port A4 port A2 port C2 port B2 port F6 port F4 port F2 end
 end
 gate Q_OR2I1 cell LOGIC
   term A port F2 end
   term B port F3 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port E2 port D1 port C1 port B1 port F5 port F1 end
   term GND port A6 port A4 port A2 port E1 port D2 port C2 port B2 port F6 port F4 end
 end
 gate Q_XOR2I0 cell LOGIC
   term A port F1 end
   term B port E2 port D1 end
   term Q port NZ end
   term VCC port F5 port F3 port E1 port C1 port B1 port A5 port A3 port A1 end
   term GND port F6 port F4 port F2 port D2 port C2 port B2 port A6 port A4 port A2 end
 end
 gate Q_MUX2X0 cell LOGIC
   term A port D1 end
   term B port E1 end
   term S port F1 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port C1 port B1 port F5 port F3 end
   term GND port A6 port A4 port A2 port E2 port D2 port C2 port B2 port F6 port F4 port F2 end
 end
 gate Q_AND2I0 cell LOGIC
   term A port A1 end
   term B port A3 end
   term Q port AZ end
   term VCC port A5 end
   term GND port A6 port A4 port A2 end
 end
 gate LOGIC2 cell LOGIC
   term A1 port A1 end
   term A2 port A2 end
   term A3 port A3 end
   term A4 port A4 end
   term A5 port A5 end
   term A6 port A6 end
   term B1 port B1 end
   term B2 port B2 end
   term C1 port C1 end
   term C2 port C2 end
   term D1 port D1 end
   term D2 port D2 end
   term E1 port E1 end
   term E2 port E2 end
   term F1 port F1 end
   term F2 port F2 end
   term F3 port F3 end
   term F4 port F4 end
   term F5 port F5 end
   term F6 port F6 end
   term MP port MP end
   term MS port MS end
   term NP port NP end
   term NS port NS end
   term OP port OP end
   term OS port OS end