ministat.edf

表决器,实现7人表决. 使用max+plus3编写. 使用简单方便.

(edif Synopsys_edif (edifVersion 2 0 0) (edifLevel 0)
 (keywordMap (keywordLevel 0))
 (status
  (written (timeStamp 1994 7 20 14 40 2)
   (program "Synopsys Design Compiler" (Version "v3.0c"))
   (dataOrigin "company") (author "designer")
  )
 )
 (external flex8000 (edifLevel 0) (technology (numberDefinition))
  (cell DFF (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port CLRN (direction INPUT)) (port PRN (direction INPUT))
     (port CLK (direction INPUT))
    )
   )
  )
  (cell TBL_1 (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port A_OUT (direction OUTPUT)) (port A_IN (direction INPUT)))
   )
  )
  (cell TBL_3 (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port A_OUT (direction OUTPUT)) (port IN1 (direction INPUT))
     (port IN2 (direction INPUT))
    )
   )
  )
  (cell TBL_2 (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port A_OUT (direction OUTPUT)) (port IN1 (direction INPUT))
     (port IN2 (direction INPUT))
    )
   )
  )
 )
 (library DESIGNS (edifLevel 0) (technology (numberDefinition))
  (cell ministat (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port reset (direction INPUT)) (port clock (direction INPUT))
     (port ps1 (direction OUTPUT)) (port ps2 (direction OUTPUT))
    )
    (contents
     (instance (rename state_reg_1_ "state_reg[1]")
      (viewRef Netlist_representation (cellRef DFF (libraryRef flex8000)))
     )
     (instance (rename state_reg_0_ "state_reg[0]")
      (viewRef Netlist_representation (cellRef DFF (libraryRef flex8000)))
     )
     (instance U40
      (viewRef Netlist_representation (cellRef TBL_1 (libraryRef flex8000)))
     )
     (instance U37
      (viewRef Netlist_representation (cellRef TBL_3 (libraryRef flex8000)))
     )
     (instance U38
      (viewRef Netlist_representation (cellRef TBL_2 (libraryRef flex8000)))
     )
     (instance U39
      (viewRef Netlist_representation (cellRef TBL_1 (libraryRef flex8000)))
     )
     (net n93
      (joined (portRef D (instanceRef state_reg_0_))
       (portRef A_OUT (instanceRef U40))
      )
     )
     (net n94
      (joined (portRef D (instanceRef state_reg_1_))
       (portRef A_OUT (instanceRef U37))
      )
     )
     (net n87
      (joined (portRef IN2 (instanceRef U37))
       (portRef A_OUT (instanceRef U39))
      )
     )
     (net n88
      (joined (portRef A_IN (instanceRef U40))
       (portRef A_OUT (instanceRef U38))
      )
     )
     (net clock
      (joined (portRef clock) (portRef CLK (instanceRef state_reg_0_))
       (portRef CLK (instanceRef state_reg_1_))
      )
     )
     (net ps1
      (joined (portRef ps1) (portRef IN1 (instanceRef U37))
       (portRef Q (instanceRef state_reg_0_))
      )
     )
     (net ps2
      (joined (portRef ps2) (portRef IN1 (instanceRef U38))
       (portRef Q (instanceRef state_reg_1_))
      )
     )
     (net reset
      (joined (portRef reset) (portRef IN2 (instanceRef U38))
       (portRef A_IN (instanceRef U39))
      )
     )
     (net VDD
      (joined (portRef CLRN (instanceRef state_reg_1_))
       (portRef PRN (instanceRef state_reg_0_))
       (portRef CLRN (instanceRef state_reg_0_))
       (portRef PRN (instanceRef state_reg_1_))
      )
     )
    )
   )
  )
 )
 (design Synopsys_edif (cellRef ministat (libraryRef DESIGNS)))
)