📄 jtd1.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jtd1 is
port(clk: in std_logic;
reset: in std_logic;
led7s: out std_logic_vector( 6 downto 0);
pout: out std_logic_vector(12 downto 1));
end jtd1;
architecture traffic of jtd1 is
signal er,ey,eg: std_logic;
signal sr,sy,sg: std_logic;
signal wr,wy,wg: std_logic;
signal nr,ny,ng: std_logic;
signal count: integer range 0 to 11;
signal state: integer range 0 to 4;
begin
process(clk,reset,count)
begin
if reset='1' then
count<=0;
state<=0;
elsif(clk'event and clk='1') then
count<=count+1;
if(count=11) then
--count<=0;
state<=state+1;
if(state>4) then
state<=0;
end if;
end if;
end if;
case state is
when 0=>ey<='1'; wy<='1'; sy<='1'; ny<='1';
eg<='0'; wg<='0'; sg<='0'; ng<='0';
er<='0'; wr<='0'; sr<='0'; nr<='0';
when 1=>ey<='0'; wy<='0'; sy<='0'; ny<='0';
eg<='1'; wg<='1'; sg<='0'; ng<='0';
er<='0'; wr<='0'; sr<='1'; nr<='1';
when 2=>ey<='1'; wy<='1'; sy<='0'; ny<='0';
eg<='1'; wg<='1'; sg<='0'; ng<='0';
er<='0'; wr<='0'; sr<='1'; nr<='1';
when 3=>ey<='0'; wy<='0'; sy<='0'; ny<='0';
eg<='0'; wg<='0'; sg<='1'; ng<='1';
er<='1'; wr<='1'; sr<='0'; nr<='0';
when 4=>ey<='0'; wy<='0'; sy<='1'; ny<='1';
eg<='0'; wg<='0'; sg<='1'; ng<='1';
er<='1'; wr<='1'; sr<='0'; nr<='0';
when others=>null;
end case;
case count is
when 0 =>led7s<="0111111";
when 1 =>led7s<="0000110";
when 2 =>led7s<="1011011";
when 3 =>led7s<="1001111";
when 4 =>led7s<="1100110";
when 5 =>led7s<="1101101";
when 6 =>led7s<="1111101";
when 7 =>led7s<="0000111";
when 8 =>led7s<="1111111";
when 9 =>led7s<="1101111";
when 10 =>led7s<="1110111";
when 11 =>led7s<="1111100";
--when "1100"=>led7s<="0111001";
--when "1101"=>led7s<="1011110";
--when "1110"=>led7s<="1111001";
--when "1111"=>led7s<="1110001";
when others => null;
end case;
end process;
pout(1)<=er; pout(2)<=eg; pout(3)<=ey;
pout(4)<=sr; pout(5)<=sg; pout(6)<=sy;
pout(7)<=wr; pout(8)<=wg; pout(9)<=wy;
pout(10)<=nr; pout(11)<=ng; pout(12)<=ny;
end traffic;
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