📄 jtd2.rpt
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_LC6_B19 = LCELL( GND);
-- Node name is '~660~1'
-- Equation name is '~660~1', location is LC1_B19, type is buried.
-- synthesized logic cell
_LC1_B19 = LCELL( _EQ017);
_EQ017 = !_LC3_B18 & state0
# !_LC3_B18 & state2;
-- Node name is ':664'
-- Equation name is '_LC2_B19', type is buried
_LC2_B19 = LCELL( _EQ018);
_EQ018 = !_LC7_B17 & state0 & !state1
# !state0 & state1
# _LC7_B17 & state1;
-- Node name is ':671'
-- Equation name is '_LC5_B19', type is buried
_LC5_B19 = LCELL( _EQ019);
_EQ019 = !state0 & state1 & !state2;
-- Node name is ':679'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = LCELL( _EQ020);
_EQ020 = !_LC7_B17 & !state0
# _LC7_B17 & state0
# _LC3_B18;
-- Node name is ':690'
-- Equation name is '_LC3_B19', type is buried
!_LC3_B19 = _LC3_B19~NOT;
_LC3_B19~NOT = LCELL( _EQ021);
_EQ021 = !state2
# !state0 & !state1;
-- Node name is '~727~1'
-- Equation name is '~727~1', location is LC8_B18, type is buried.
-- synthesized logic cell
_LC8_B18 = LCELL( _EQ022);
_EQ022 = state0 & state2
# state1 & state2
# _LC7_B20 & !state0 & !state2;
-- Node name is '~1014~1'
-- Equation name is '~1014~1', location is LC3_C17, type is buried.
-- synthesized logic cell
_LC3_C17 = LCELL( _EQ023);
_EQ023 = state2
# state0 & state1;
-- Node name is '~1014~2'
-- Equation name is '~1014~2', location is LC6_C17, type is buried.
-- synthesized logic cell
_LC6_C17 = LCELL( _EQ024);
_EQ024 = state2
# state0 & state1;
-- Node name is '~1014~3'
-- Equation name is '~1014~3', location is LC2_C17, type is buried.
-- synthesized logic cell
_LC2_C17 = LCELL( _EQ025);
_EQ025 = state2
# state0 & state1;
-- Node name is ':1014'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = LCELL( _EQ026);
_EQ026 = state2
# state0 & state1;
-- Node name is '~1074~1'
-- Equation name is '~1074~1', location is LC5_C17, type is buried.
-- synthesized logic cell
_LC5_C17 = LCELL( _EQ027);
_EQ027 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is '~1074~2'
-- Equation name is '~1074~2', location is LC6_B18, type is buried.
-- synthesized logic cell
_LC6_B18 = LCELL( _EQ028);
_EQ028 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is '~1074~3'
-- Equation name is '~1074~3', location is LC4_C17, type is buried.
-- synthesized logic cell
_LC4_C17 = LCELL( _EQ029);
_EQ029 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is ':1074'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = LCELL( _EQ030);
_EQ030 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is ':1316'
-- Equation name is '_LC6_B20', type is buried
!_LC6_B20 = _LC6_B20~NOT;
_LC6_B20~NOT = LCELL( _EQ031);
_EQ031 = count3
# !count2
# count1
# !count0;
-- Node name is ':1357'
-- Equation name is '_LC8_B20', type is buried
_LC8_B20 = LCELL( _EQ032);
_EQ032 = !count1 & count3
# !count1 & !count2
# count2 & count3
# count1 & count2
# count0 & !count1
# !count0 & !count2 & !count3
# !count0 & count1 & !count3
# count0 & count3
# count0 & count2;
-- Node name is ':1381'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = LCELL( _EQ033);
_EQ033 = !_LC4_B20 & _LC8_B20
# !_LC4_B20 & _LC7_B20;
-- Node name is ':1415'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ034);
_EQ034 = count2 & count3
# !count1 & count3
# count0 & count3
# count0 & count1
# !count0 & !count1 & !count2;
-- Node name is ':1451'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = LCELL( _EQ035);
_EQ035 = count0 & count3
# count2 & count3
# count0 & count1 & !count2
# count1 & !count2 & !count3
# !count0 & !count2 & !count3
# count0 & !count1 & count2;
-- Node name is ':1487'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = LCELL( _EQ036);
_EQ036 = count0 & count3
# count2 & count3
# !count1 & count3
# !count0 & count1 & count2
# !count0 & count1 & !count3
# count0 & count1 & !count2
# count1 & !count2 & !count3
# !count0 & !count2 & !count3
# !count0 & !count1 & !count2
# count0 & !count1 & count2;
-- Node name is ':1523'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ037);
_EQ037 = _LC4_B20
# !_LC6_B20 & !_LC7_B20;
-- Node name is '~1559~1'
-- Equation name is '~1559~1', location is LC4_B20, type is buried.
-- synthesized logic cell
_LC4_B20 = LCELL( _EQ038);
_EQ038 = !count1 & !count2 & !count3;
-- Node name is ':1559'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ039);
_EQ039 = count1
# count2
# !count3;
-- Node name is ':1595'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ040);
_EQ040 = count3
# !count0 & count1
# count1 & !count2
# !count0 & !count2
# count0 & !count1 & count2;
-- Node name is ':1846'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ041);
_EQ041 = clk & !state0 & !state2;
-- Node name is ':1919'
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = LCELL( _EQ042);
_EQ042 = clk & state2
# clk & !state0 & !state1;
-- Node name is ':1992'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ043);
_EQ043 = clk & !state0 & !state2;
-- Node name is ':2065'
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = LCELL( _EQ044);
_EQ044 = clk & state2
# clk & !state0 & !state1;
Project Information e:\eda\jiaotongdeng\jtd2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,255K
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