📄 jtd2.rpt
字号:
- 1 - B 19 OR2 s 0 3 0 2 ~660~1
- 2 - B 19 OR2 0 3 0 1 :664
- 5 - B 19 AND2 0 3 0 1 :671
- 7 - B 18 OR2 0 3 0 1 :679
- 3 - B 19 OR2 ! 0 3 0 2 :690
- 8 - B 18 OR2 s 0 4 0 1 ~727~1
- 3 - C 17 OR2 s 0 3 1 0 ~1014~1
- 6 - C 17 OR2 s 0 3 1 0 ~1014~2
- 2 - C 17 OR2 s 0 3 1 0 ~1014~3
- 5 - B 18 OR2 0 3 1 0 :1014
- 5 - C 17 OR2 s 0 3 1 0 ~1074~1
- 6 - B 18 OR2 s 0 3 1 0 ~1074~2
- 4 - C 17 OR2 s 0 3 1 0 ~1074~3
- 7 - C 17 OR2 0 3 1 0 :1074
- 6 - B 20 OR2 ! 0 4 0 1 :1316
- 8 - B 20 OR2 0 4 0 1 :1357
- 3 - B 20 OR2 0 3 1 0 :1381
- 1 - B 24 OR2 0 4 1 0 :1415
- 1 - B 20 OR2 0 4 1 0 :1451
- 5 - B 20 OR2 0 4 1 0 :1487
- 2 - B 20 OR2 0 3 1 0 :1523
- 4 - B 20 AND2 s 0 3 0 2 ~1559~1
- 3 - B 24 OR2 0 3 1 0 :1559
- 6 - B 24 OR2 0 4 1 0 :1595
- 4 - A 13 AND2 1 2 1 0 :1846
- 1 - C 17 OR2 1 3 1 0 :1919
- 1 - A 13 AND2 1 2 1 0 :1992
- 8 - C 17 OR2 1 3 1 0 :2065
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\jiaotongdeng\jtd2.rpt
jtd2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 10/ 96( 10%) 0/ 48( 0%) 13/ 48( 27%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\jiaotongdeng\jtd2.rpt
jtd2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: e:\eda\jiaotongdeng\jtd2.rpt
jtd2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: e:\eda\jiaotongdeng\jtd2.rpt
jtd2
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':25' = 'count0'
-- Equation name is 'count0', location is LC4_B18, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = _LC3_B18 & state0
# _LC3_B18 & state2
# _LC2_B18;
-- Node name is ':24' = 'count1'
-- Equation name is 'count1', location is LC1_B17, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = _LC6_B17 & state0
# _LC6_B17 & state2
# _LC8_B17;
-- Node name is ':23' = 'count2'
-- Equation name is 'count2', location is LC2_B17, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = count2 & !_LC4_B17 & _LC5_B17
# !count2 & _LC4_B17 & _LC5_B17;
-- Node name is ':22' = 'count3'
-- Equation name is 'count3', location is LC3_B17, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = !count2 & count3 & _LC5_B17
# count3 & !_LC4_B17 & _LC5_B17
# count2 & !count3 & _LC4_B17 & _LC5_B17;
-- Node name is 'led7s0'
-- Equation name is 'led7s0', type is output
led7s0 = _LC6_B24;
-- Node name is 'led7s1'
-- Equation name is 'led7s1', type is output
led7s1 = _LC3_B24;
-- Node name is 'led7s2'
-- Equation name is 'led7s2', type is output
led7s2 = _LC2_B20;
-- Node name is 'led7s3'
-- Equation name is 'led7s3', type is output
led7s3 = _LC5_B20;
-- Node name is 'led7s4'
-- Equation name is 'led7s4', type is output
led7s4 = _LC1_B20;
-- Node name is 'led7s5'
-- Equation name is 'led7s5', type is output
led7s5 = _LC1_B24;
-- Node name is 'led7s6'
-- Equation name is 'led7s6', type is output
led7s6 = _LC3_B20;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC5_B18;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC7_C17;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC4_A13;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC5_C17;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC3_C17;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
pout6 = _LC1_C17;
-- Node name is 'pout7'
-- Equation name is 'pout7', type is output
pout7 = _LC6_C17;
-- Node name is 'pout8'
-- Equation name is 'pout8', type is output
pout8 = _LC6_B18;
-- Node name is 'pout9'
-- Equation name is 'pout9', type is output
pout9 = _LC1_A13;
-- Node name is 'pout10'
-- Equation name is 'pout10', type is output
pout10 = _LC4_C17;
-- Node name is 'pout11'
-- Equation name is 'pout11', type is output
pout11 = _LC2_C17;
-- Node name is 'pout12'
-- Equation name is 'pout12', type is output
pout12 = _LC8_C17;
-- Node name is ':28' = 'state0'
-- Equation name is 'state0', location is LC1_B18, type is buried.
state0 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = _LC7_B18 & state0
# _LC7_B18 & state2
# _LC8_B18;
-- Node name is ':27' = 'state1'
-- Equation name is 'state1', location is LC8_B19, type is buried.
state1 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = _LC1_B19 & _LC2_B19 & !_LC3_B19
# !_LC3_B19 & _LC5_B19;
-- Node name is ':26' = 'state2'
-- Equation name is 'state2', location is LC4_B19, type is buried.
state2 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = !_LC3_B19 & _LC6_B19
# _LC1_B19 & !_LC3_B19 & _LC7_B19;
-- Node name is '|LPM_ADD_SUB:425|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B17', type is buried
!_LC4_B17 = _LC4_B17~NOT;
_LC4_B17~NOT = LCELL( _EQ008);
_EQ008 = !count1
# !count0;
-- Node name is ':465'
-- Equation name is '_LC3_B18', type is buried
!_LC3_B18 = _LC3_B18~NOT;
_LC3_B18~NOT = LCELL( _EQ009);
_EQ009 = !state2
# !_LC7_B20
# state0
# state1;
-- Node name is ':470'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = LCELL( _EQ010);
_EQ010 = !count3
# !count2 & !_LC4_B17;
-- Node name is ':497'
-- Equation name is '_LC7_B20', type is buried
!_LC7_B20 = _LC7_B20~NOT;
_LC7_B20~NOT = LCELL( _EQ011);
_EQ011 = count3
# !count1
# count0
# count2;
-- Node name is '~610~1'
-- Equation name is '~610~1', location is LC5_B17, type is buried.
-- synthesized logic cell
_LC5_B17 = LCELL( _EQ012);
_EQ012 = !_LC3_B18 & _LC7_B17
# !state0 & !state2;
-- Node name is ':631'
-- Equation name is '_LC6_B17', type is buried
_LC6_B17 = LCELL( _EQ013);
_EQ013 = !count0 & count1 & _LC7_B17
# count0 & !count1 & _LC7_B17
# _LC3_B18;
-- Node name is ':635'
-- Equation name is '_LC8_B17', type is buried
_LC8_B17 = LCELL( _EQ014);
_EQ014 = !count0 & count1 & !state0 & !state2
# count0 & !count1 & !state0 & !state2;
-- Node name is '~646~1'
-- Equation name is '~646~1', location is LC2_B18, type is buried.
-- synthesized logic cell
_LC2_B18 = LCELL( _EQ015);
_EQ015 = !count0 & !state0 & !state2
# !count0 & _LC7_B17;
-- Node name is ':652'
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = LCELL( _EQ016);
_EQ016 = !state0 & state2
# !state1 & state2
# !_LC7_B17 & state0 & state1 & !state2
# _LC7_B17 & state2;
-- Node name is ':659'
-- Equation name is '_LC6_B19', type is buried
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