📄 jtd0.rpt
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FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\jiaotongdeng\jtd0.rpt
jtd0
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 clk
Device-Specific Information: e:\eda\jiaotongdeng\jtd0.rpt
jtd0
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: e:\eda\jiaotongdeng\jtd0.rpt
jtd0
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':18' = 'count0'
-- Equation name is 'count0', location is LC7_B19, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
-- Node name is ':17' = 'count1'
-- Equation name is 'count1', location is LC6_B19, type is buried.
count1 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = count0 & !count1
# !count0 & count1;
-- Node name is ':16' = 'count2'
-- Equation name is 'count2', location is LC5_B19, type is buried.
count2 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = !count0 & count2
# !count1 & count2
# count0 & count1 & !count2;
-- Node name is ':15' = 'count3'
-- Equation name is 'count3', location is LC4_B19, type is buried.
count3 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = !count2 & count3
# !count0 & count3
# !count1 & count3
# count0 & count1 & count2 & !count3;
-- Node name is 'pout1'
-- Equation name is 'pout1', type is output
pout1 = _LC4_B18;
-- Node name is 'pout2'
-- Equation name is 'pout2', type is output
pout2 = _LC5_B18;
-- Node name is 'pout3'
-- Equation name is 'pout3', type is output
pout3 = _LC6_B23;
-- Node name is 'pout4'
-- Equation name is 'pout4', type is output
pout4 = _LC5_B23;
-- Node name is 'pout5'
-- Equation name is 'pout5', type is output
pout5 = _LC3_B18;
-- Node name is 'pout6'
-- Equation name is 'pout6', type is output
pout6 = _LC8_B18;
-- Node name is 'pout7'
-- Equation name is 'pout7', type is output
pout7 = _LC1_B18;
-- Node name is 'pout8'
-- Equation name is 'pout8', type is output
pout8 = _LC2_B23;
-- Node name is 'pout9'
-- Equation name is 'pout9', type is output
pout9 = _LC1_B23;
-- Node name is 'pout10'
-- Equation name is 'pout10', type is output
pout10 = _LC2_B18;
-- Node name is 'pout11'
-- Equation name is 'pout11', type is output
pout11 = _LC6_B18;
-- Node name is 'pout12'
-- Equation name is 'pout12', type is output
pout12 = _LC7_B18;
-- Node name is ':21' = 'state0'
-- Equation name is 'state0', location is LC3_B19, type is buried.
state0 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = !_LC8_B19 & state0
# _LC8_B19 & !state0 & !state1
# _LC8_B19 & !state0 & !state2;
-- Node name is ':20' = 'state1'
-- Equation name is 'state1', location is LC1_B19, type is buried.
state1 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = !_LC8_B19 & state1
# _LC8_B19 & state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is ':19' = 'state2'
-- Equation name is 'state2', location is LC2_B19, type is buried.
state2 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = !state0 & !state1 & state2
# _LC8_B19 & state0 & state1 & !state2
# !_LC8_B19 & state2;
-- Node name is ':310'
-- Equation name is '_LC8_B19', type is buried
_LC8_B19 = LCELL( _EQ007);
_EQ007 = count0 & count1 & !count2 & count3;
-- Node name is ':588'
-- Equation name is '_LC6_B23', type is buried
!_LC6_B23 = _LC6_B23~NOT;
_LC6_B23~NOT = LCELL( _EQ008);
_EQ008 = state0
# state2;
-- Node name is ':603'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = LCELL( _EQ009);
_EQ009 = !state0 & !state2;
-- Node name is ':618'
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = LCELL( _EQ010);
_EQ010 = state2
# !state0 & !state1;
-- Node name is ':633'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = LCELL( _EQ011);
_EQ011 = state2
# !state0 & !state1;
-- Node name is '~695~1'
-- Equation name is '~695~1', location is LC3_B18, type is buried.
-- synthesized logic cell
_LC3_B18 = LCELL( _EQ012);
_EQ012 = state2
# state0 & state1;
-- Node name is '~695~2'
-- Equation name is '~695~2', location is LC1_B18, type is buried.
-- synthesized logic cell
_LC1_B18 = LCELL( _EQ013);
_EQ013 = state2
# state0 & state1;
-- Node name is '~695~3'
-- Equation name is '~695~3', location is LC6_B18, type is buried.
-- synthesized logic cell
_LC6_B18 = LCELL( _EQ014);
_EQ014 = state2
# state0 & state1;
-- Node name is ':695'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = LCELL( _EQ015);
_EQ015 = state2
# state0 & state1;
-- Node name is '~755~1'
-- Equation name is '~755~1', location is LC5_B23, type is buried.
-- synthesized logic cell
_LC5_B23 = LCELL( _EQ016);
_EQ016 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is '~755~2'
-- Equation name is '~755~2', location is LC2_B23, type is buried.
-- synthesized logic cell
_LC2_B23 = LCELL( _EQ017);
_EQ017 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is '~755~3'
-- Equation name is '~755~3', location is LC2_B18, type is buried.
-- synthesized logic cell
_LC2_B18 = LCELL( _EQ018);
_EQ018 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
-- Node name is ':755'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = LCELL( _EQ019);
_EQ019 = state0 & !state1 & !state2
# !state0 & state1 & !state2;
Project Information e:\eda\jiaotongdeng\jtd0.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,140K
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