📄 main.lss
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AT91F_PWMC_StopChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID4); // Disable PWM on channel 2 (PWM2 = PA25 = buzzer)
while(AT91C_BASE_PWMC->PWMC_SR & AT91C_PWMC_CHID4); //wait for disabled
10050c: 68cb ldr r3, [r1, #12] 10050e: 4213 tst r3, r2 100510: d1fc bne 10050c <main+0x2d8> AT91C_BASE_PWMC_CH4->PWMC_CPRDR = (MCK * PERIOD_CH0) / (2 * PWM_PRESCALE); // Re-configure period
100512: 22f0 mov r2, #240 100514: 4b4c ldr r3, [pc, #304] (100648 <.text+0x648>) 100516: 609a str r2, [r3, #8] AT91C_BASE_PWMC_CH4->PWMC_CDTYR = ((MCK * PERIOD_CH0) / (2 * PWM_PRESCALE)) * (adval/1024.0); // Re-configure duty cycle
100518: 1c30 mov r0, r6 (add r0, r6, #0) 10051a: facdf004 bl 104ab8 <__floatsidf> 10051e: 2e00 cmp r6, #0 100520: da03 bge 10052a <main+0x2f6> 100522: 4a4a ldr r2, [pc, #296] (10064c <.text+0x64c>) 100524: 4b4a ldr r3, [pc, #296] (100650 <.text+0x650>) 100526: f929f004 bl 10477c <__adddf3> 10052a: 4a4a ldr r2, [pc, #296] (100654 <.text+0x654>) 10052c: 4b4a ldr r3, [pc, #296] (100658 <.text+0x658>) 10052e: f95df004 bl 1047ec <__muldf3> 100532: 4a4a ldr r2, [pc, #296] (10065c <.text+0x65c>) 100534: 4b4a ldr r3, [pc, #296] (100660 <.text+0x660>) 100536: f959f004 bl 1047ec <__muldf3> 10053a: ff87f003 bl 10444c <__fixunsdfsi> 10053e: 4b42 ldr r3, [pc, #264] (100648 <.text+0x648>) 100540: 6058 str r0, [r3, #4]__inline void AT91F_PWMC_StartChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg Channels IDs to be enabled
{
pPWM->PWMC_ENA = flag;
100542: 2210 mov r2, #16 100544: 4b1a ldr r3, [pc, #104] (1005b0 <.text+0x5b0>) 100546: 605a str r2, [r3, #4] 100548: 2100 mov r1, #0 10054a: e6ef b 10032c <main+0xf8>}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_StopChannel
//* \brief Disable channel
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_StopChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg Channels IDs to be enabled
{
pPWM->PWMC_DIS = flag;
10054c: 2210 mov r2, #16 10054e: 4b18 ldr r3, [pc, #96] (1005b0 <.text+0x5b0>) 100550: 609a str r2, [r3, #8] 100552: 1c18 mov r0, r3 (add r0, r3, #0) 100554: 2110 mov r1, #16 AT91F_PWMC_StartChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID4); // Re-enable PWM on channel 2 (PWM2 = PA25 =
break;
case 7 :
AT91F_PWMC_StopChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID4); // Disable PWM on channel 2 (PWM2 = PA25 = buzzer)
while(AT91C_BASE_PWMC->PWMC_SR & AT91C_PWMC_CHID4); //wait for disabled
100556: 68c3 ldr r3, [r0, #12] 100558: 420b tst r3, r1 10055a: d1fc bne 100556 <main+0x322> AT91C_BASE_PWMC_CH4->PWMC_CPRDR = (MCK * PERIOD_CH0) / (2 * PWM_PRESCALE); // Re-configure period
10055c: 4b3a ldr r3, [pc, #232] (100648 <.text+0x648>) 10055e: 22f0 mov r2, #240 100560: 609a str r2, [r3, #8] AT91C_BASE_PWMC_CH4->PWMC_CDTYR = ((MCK * PERIOD_CH0) / (2 * PWM_PRESCALE)) * 0.85; // Re-configure duty cycle
100562: 22cc mov r2, #204 100564: 605a str r2, [r3, #4]__inline void AT91F_PWMC_StartChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg Channels IDs to be enabled
{
pPWM->PWMC_ENA = flag;
100566: 6041 str r1, [r0, #4] 100568: 2100 mov r1, #0 10056a: e6df b 10032c <main+0xf8>}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_StopChannel
//* \brief Disable channel
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_StopChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg Channels IDs to be enabled
{
pPWM->PWMC_DIS = flag;
10056c: 2210 mov r2, #16 10056e: 4b10 ldr r3, [pc, #64] (1005b0 <.text+0x5b0>) 100570: 609a str r2, [r3, #8] 100572: 1c18 mov r0, r3 (add r0, r3, #0) 100574: 2110 mov r1, #16 AT91F_PWMC_StartChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID4); // Re-enable PWM on channel 2 (PWM2 = PA25 =
break;
case 8 :
AT91F_PWMC_StopChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID4); // Disable PWM on channel 2 (PWM2 = PA25 = buzzer)
while(AT91C_BASE_PWMC->PWMC_SR & AT91C_PWMC_CHID4); //wait for disabled
100576: 68c3 ldr r3, [r0, #12] 100578: 420b tst r3, r1 10057a: d1fc bne 100576 <main+0x342>
AT91C_BASE_PWMC_CH4->PWMC_CPRDR = (MCK * PERIOD_CH0) / (2 * PWM_PRESCALE); // Re-configure period
10057c: 4b32 ldr r3, [pc, #200] (100648 <.text+0x648>) 10057e: 22f0 mov r2, #240 100580: 609a str r2, [r3, #8] AT91C_BASE_PWMC_CH4->PWMC_CDTYR = ((MCK * PERIOD_CH0) / (2 * PWM_PRESCALE)) * 0.25; // Re-configure duty cycle
100582: 223c mov r2, #60 100584: 605a str r2, [r3, #4]__inline void AT91F_PWMC_StartChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg Channels IDs to be enabled
{
pPWM->PWMC_ENA = flag;
100586: 6041 str r1, [r0, #4] 100588: 2100 mov r1, #0 10058a: e6cf b 10032c <main+0xf8> AT91F_PWMC_StartChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID4); // Re-enable PWM on channel 2 (PWM2 = PA25 = buzzer)
break;
default:
iprintf("Invalid Choice\n\r");
10058c: 4835 ldr r0, [pc, #212] (100664 <.text+0x664>) 10058e: fb19f000 bl 100bc4 <iprintf> 100592: 2100 mov r1, #0 100594: e6ca b 10032c <main+0xf8> 100596: 0000 lsl r0, r0, #0 100598: 0401 lsl r1, r0, #16 10059a: a500 add r5, pc, #0 (adr r5,10059c <.text+0x59c>) 10059c: fd00 second half of BL instruction 0xfd00 10059e: ffff second half of BL instruction 0xffff 1005a0: fc00 second half of BL instruction 0xfc00 1005a2: ffff second half of BL instruction 0xffff 1005a4: fffff400 bl ffd015a6 <__TOP_STACK+0xffaf15a6> 1005a8: 1041 asr r1, r0, #1 1005aa: 0000 lsl r0, r0, #0 1005ac: fffff600 bl fff015ae <__TOP_STACK+0xffcf15ae> 1005b0: c000 stmia r0!,{} 1005b2: fffc second half of BL instruction 0xfffc 1005b4: 0302 lsl r2, r0, #12 1005b6: 0000 lsl r0, r0, #0 1005b8: 0702 lsl r2, r0, #28 1005ba: 0000 lsl r0, r0, #0 1005bc: 01c9 lsl r1, r1, #7 1005be: 0020 lsl r0, r4, #0 1005c0: fffff000 bl 1015c2 <_vfiprintf_r+0x1be> 1005c4: 27c0 mov r7, #192 1005c6: 0309 lsl r1, r1, #12 1005c8: fd30 second half of BL instruction 0xfd30 1005ca: ffff second half of BL instruction 0xffff 1005cc: 56a0 ldrsb r0, [r4, r2] 1005ce: 0010 lsl r0, r2, #0 1005d0: 56cc ldrsb r4, [r1, r3] 1005d2: 0010 lsl r0, r2, #0 1005d4: 6c00 ldr r0, [r0, #64] 1005d6: 02dc lsl r4, r3, #11 1005d8: 56ec ldrsb r4, [r5, r3] 1005da: 0010 lsl r0, r2, #0 1005dc: fc10 second half of BL instruction 0xfc10 1005de: ffff second half of BL instruction 0xffff 1005e0: 0a28 lsr r0, r5, #8 1005e2: 0020 lsl r0, r4, #0 1005e4: 5728 ldrsb r0, [r5, r4] 1005e6: 0010 lsl r0, r2, #0 1005e8: 573c ldrsb r4, [r7, r4] 1005ea: 0010 lsl r0, r2, #0 1005ec: 574c ldrsb r4, [r1, r5] 1005ee: 0010 lsl r0, r2, #0 1005f0: 575c ldrsb r4, [r3, r5] 1005f2: 0010 lsl r0, r2, #0 1005f4: 576c ldrsb r4, [r5, r5] 1005f6: 0010 lsl r0, r2, #0 1005f8: 577c ldrsb r4, [r7, r5] 1005fa: 0010 lsl r0, r2, #0 1005fc: 578c ldrsb r4, [r1, r6] 1005fe: 0010 lsl r0, r2, #0 100600: 579c ldrsb r4, [r3, r6] 100602: 0010 lsl r0, r2, #0 100604: 57ac ldrsb r4, [r5, r6] 100606: 0010 lsl r0, r2, #0 100608: 57bc ldrsb r4, [r7, r6] 10060a: 0010 lsl r0, r2, #0 10060c: 57c8 ldrsb r0, [r1, r7] 10060e: 0010 lsl r0, r2, #0 100610: 01fc lsl r4, r7, #7 100612: 0020 lsl r0, r4, #0 100614: 57e4 ldrsb r4, [r4, r7] 100616: 0010 lsl r0, r2, #0 100618: 57e8 ldrsb r0, [r5, r7] 10061a: 0010 lsl r0, r2, #0 10061c: 58bc ldr r4, [r7, r2] 10061e: 0010 lsl r0, r2, #0 100620: 03ff lsl r7, r7, #15 100622: 0000 lsl r0, r0, #0 100624: 57f8 ldrsb r0, [r7, r7] 100626: 0010 lsl r0, r2, #0 100628: 7530 strb r0, [r6, #20] 10062a: 0000 lsl r0, r0, #0 10062c: 2710 mov r7, #16 10062e: 0000 lsl r0, r0, #0 100630: 5824 ldr r4, [r4, r0] 100632: 0010 lsl r0, r2, #0 100634: 5850 ldr r0, [r2, r1] 100636: 0010 lsl r0, r2, #0 100638: 587c ldr r4, [r7, r1] 10063a: 0010 lsl r0, r2, #0 10063c: 58e0 ldr r0, [r4, r3] 10063e: 0010 lsl r0, r2, #0 100640: 58ec ldr r4, [r5, r3] 100642: 0010 lsl r0, r2, #0 100644: 58dc ldr r4, [r3, r3] 100646: 0010 lsl r0, r2, #0 100648: c280 stmia r2!,{r7} 10064a: fffc second half of BL instruction 0xfffc 10064c: 0000 lsl r0, r0, #0 10064e: 41f0 ror r0, r6 100650: 0000 lsl r0, r0, #0 100652: 0000 lsl r0, r0, #0 100654: 0000 lsl r0, r0, #0 100656: 3f50 sub r7, #80 100658: 0000 lsl r0, r0, #0 10065a: 0000 lsl r0, r0, #0 10065c: 0000 lsl r0, r0, #0 10065e: 406e eor r6, r5 100660: 0000 lsl r0, r0, #0 100662: 0000 lsl r0, r0, #0 100664: 58a8 ldr r0, [r5, r2] 100666: 0010 lsl r0, r2, #000100668 <AT91F_DBGU_Init>: unsigned int periphAEnable, // \arg PERIPH A to enable
unsigned int periphBEnable) // \arg PERIPH B to enable
{
pPio->PIO_ASR = periphAEnable;
100668: 4a14 ldr r2, [pc, #80] (1006bc <.text+0x6bc>) 10066a: 23c0 mov r3, #192 10066c: 061b lsl r3, r3, #24 10066e: 6713 str r3, [r2, #112] pPio->PIO_BSR = periphBEnable;
100670: 2100 mov r1, #0 100672: 6751 str r1, [r2, #116] pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
100674: 6053 str r3, [r2, #4]}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgOutput
//* \brief Enable PIO in output mode
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgOutput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int pioEnable) // \arg PIO to be enabled
{
pPio->PIO_PER = pioEnable; // Set in PIO mode
pPio->PIO_OER = pioEnable; // Configure in Output
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgInput
//* \brief Enable PIO in input mode
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgInput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int inputEnable) // \arg PIO to be enabled
{
// Disable output
pPio->PIO_ODR = inputEnable;
pPio->PIO_PER = inputEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgOpendrain
//* \brief Configure PIO in open drain
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgOpendrain(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int multiDrvEnable) // \arg pio to be configured in open drain
{
// Configure the multi-drive option
pPio->PIO_MDDR = ~multiDrvEnable;
pPio->PIO_MDER = multiDrvEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgPullup
//* \brief Enable pullup on PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgPullup(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int pullupEnable) // \arg enable pullup on PIO
{
// Connect or not Pullup
pPio->PIO_PPUDR = ~pullupEnable;
pPio->PIO_PPUER = pullupEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgDirectDrive
//* \brief Enable direct drive on PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgDirectDrive(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int directDrive) // \arg PIO to be configured with direct drive
{
// Configure the Direct Drive
pPio->PIO_OWDR = ~directDrive;
pPio->PIO_OWER = directDrive;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgInputFilter
//* \brief Enable input filter on input PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgInputFilter(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int inputFilter) // \arg PIO to be configured with input filter
{
// Configure the Direct Drive
pPio->PIO_IFDR = ~inputFilter;
pPio->PIO_IFER = inputFilter;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetInput
//* \brief Return PIO input value
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
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