start.s

著名的嵌入式操作系统Nucleus的源代码

;
; Startup Code for EP7212 with JTAG emulator
;
SYSCFG			EQU		&3FF0000
LOCKOUT			EQU		&C0		; Interrupt lockout value
LOCK_MSK		EQU		&C0		; Interrupt lockout mask value
MODE_MASK		EQU		&1F		; Processor Mode Mask
SUP_MODE		EQU		&13		; Supervisor Mode (SVC)
IRQ_MODE		EQU     &12				; Interrupt Mode (IRQ)
FIQ_MODE		EQU     &11				; Fast Interrupt Mode (FIQ)
IRQEN			EQU	&7f				;And this value will enable IRQ
FIQEN			EQU	&bf				;and this value will enable FIQ
	IMPORT	INT_Initialize
	IMPORT	|Image$$ZI$$Base|
	IMPORT	|Image$$ZI$$Limit|
	IMPORT	|Image$$RO$$Limit|
	IMPORT	|Image$$RW$$Base|
	IMPORT	|C$$data$$Base|
	IMPORT	|C$$data$$Limit|

	IMPORT	INT_UNDEFINE
;	IMPORT	INT_SWI_PARSE
;	IMPORT	INT_PREF_ABORT
;	IMPORT	INT_DATA_ABORT
	IMPORT	INT_IRQ_PARSE
	IMPORT	INT_FIQ_PARSE

        GBLL    THUMB
        GBLL    ARM
    [ {CONFIG} = 16
THUMB   SETL    {TRUE}
ARM     SETL    {FALSE}

; If assembling with TASM go into 32 bit mode as the Armulator will
; start up the program in ARM state.

        CODE32
    |
THUMB   SETL    {FALSE}
ARM     SETL    {TRUE}
    ]





	


;************************************************************************
; Use the name "!!!" for the CODE SECTION name so that this linker will
; place this area first (the linker sorts areas within a given type, eg.
; CODE, DATA, BSS, alphabetically by name so "!!!" ensures this comes
; first).
;************************************************************************
        [ THUMB
	AREA |!!!code|, CODE, READONLY,INTERWORK
        |
	AREA |!!!code|, CODE, READONLY
        ]

		ENTRY

;************************************************************************
; First instruction to be executed.
;
; Branch to the HdwInit entry point in the BSP.
;
; Following the RESET branch are branches for all the remaining vectors.
; A real target might run with ROM always mapped to location 0,
; in which case we need to have branches at the vector locations.
;************************************************************************

;WTXCHG1
dder
		LDR		pc, (Vect_Table)		; Reset vector
;WTXCHG1		
		LDR		pc, (Vect_Table + 4)		; Undefined instruction
		LDR		pc, (Vect_Table + 8)		; SWI
		LDR		pc, (Vect_Table +12)		; Prefetch abort
		LDR		pc, (Vect_Table +16)		; Data abort
;WTXCHG2
		;b		infinit_loop			; Address exception
		LDR		pc, (Vect_Table +20)
;WTXCHG2
		LDR		pc, (Vect_Table +24)		; IRQ
		LDR		pc, (Vect_Table +28)		; FIQ

Vect_Table
		DCD		startup
		DCD		INT_UNDEFINE
		DCD		INT_UNDEFINE
		DCD		INT_UNDEFINE
		DCD		INT_UNDEFINE
		DCD		INT_UNDEFINE
		DCD		INT_IRQ_PARSE
		DCD		INT_FIQ_PARSE

;        [ THUMB
;	AREA |C$$code|, CODE, READONLY,INTERWORK
;        |
;	AREA |C$$code|, CODE, READONLY
;       ]

startup
		EXPORT  main
main
		MRS		a1,CPSR					; Pickup current CPSR
		BIC		a1,a1,#MODE_MASK		; Clear the mode bits
		ORR		a1,a1,#SUP_MODE			; Set the supervisor mode bits
		ORR		a1,a1,#LOCKOUT			; Insure IRQ and FIQ intr are locked out
		MSR		CPSR_cxsf,a1			; Setup the new CPSR
;
; H/W init already finished by emulator or init module
;

;Now the follow is special for KS32c50100
		LDR     r0, =SYSCFG		 
        	LDR     r1, =0x7FFFF90          ; Start_addr = 0x3FF00000
        	STR     r1, [r0]                ; Cache OFF, Write Buffer OFF
		
		ADRL		r0,SysSetting
		LDMIA		r0,{r1-r12}
		LDR		r0,=0x3ff0000+0x3010		;put the address of extdbwth into r0
		STMIA		r0,{r1-r12}			;Set the extdbwth and each bank control register
		



;
; Clear the un-initialized global and static C data areas
;
		LDR		a1,=|Image$$ZI$$Base|	; Pickup the start of the BSS area
		MOV		a3,#0			; Clear value in a3
		LDR		a2,=|Image$$ZI$$Limit|	; Pickup the end of the BSS area
		CMP		a1,a2
		BEQ		move_data
clear_loop
		STR		a3,[a1],#4				; Clear a word, a1 += 4
		CMP		a1,a2					; end of ZI ?
		BNE		clear_loop				; If not, continue with the BSS clear
;
; Move the initialized global and initialized C data areas
;
move_data
		LDR		a1,=|Image$$RW$$Base|	; Pickup the start of the DATA area
		LDR		a2,=|Image$$RO$$Limit|	; Pickup the end of the CODE area
		LDR		a3,=|Image$$ZI$$Base|	; Pickup the start of the BSS area
		CMP		a1,a3
		BEQ		goto_main
move_loop
		LDR		a4,[a2],#4
		STR		a4,[a1],#4				; move a word, a1 += 4, a2 += 4
		CMP		a1,a3					; end of DATA ?
		BNE		move_loop				; If not, continue with the BSS clear

;Now set the system stack point
	;	LDR     a1,=|Image$$ZI$$Limit|          ; Pickup the ending address of BSS
	;	MOV     a2,#4096                 	; Pickup system stack size
	;	SUB     a2,a2,#4                        ; Subtract one word for first addr
	;	ADD     a3,a1,a2                        ; Build start of system stack area
	;	BIC     a3,a3,#3                        ; Insure word aligment of stack
	;	MOV     sp,a3                           ; Setup initial stack pointer
		
;Now set IRQ stack point
	;	MOV	a2,#1024	
	;	add	a3,a3,a2
	;	BIC     a3,a3,#3 	
	;	MRS	a1,CPSR					; Pickup current CPSR
	;	BIC	a1,a1,#MODE_MASK		; Clear the mode bits
	;	ORR	a1,a1,#IRQ_MODE			; Set the supervisor mode bits
	;	ORR	a1,a1,#LOCKOUT			; Insure IRQ and FIQ intr are locked out
	;	MSR	CPSR_cxsf,a1			; Setup the new CPSR
	;	MOV     sp,a3 





goto_main
		LDR		pc,=INT_Initialize
		
		
		;B      main_start
		
		
		


SysSetting
	DCD 0x0ffffffe		;EXTDBWTH
	DCD 0x18860040		;ROMCON0
	DCD 0x00400040		;ROMCON1
	DCD 0x00801040		;ROMCON2
	DCD 0x00902040		;ROMCON3
	DCD 0x00a02440		;ROMCON4
	DCD 0x00b02840		;ROMCON5
	DCD 0x00c02c40		;DRAMCON0
	DCD 0x00d03040		;DRAMCON1
	DCD 0x00e03440		;DRAMCON2
	DCD 0x00f03840		;DRAMCON3
	DCD 0x00008010		;REFEXTCON


		END