dec643_flash.c

dm643扩展flash的测试程序 基于CSL

/********************************************************************/
/*  Copyright 2004 by SEED Incorporated.							*/
/*  All rights reserved. Property of SEED Incorporated.				*/
/*  Restricted rights to use, duplicate or disclose this code are	*/
/*  granted through contract.									    */
/*  															    */
/********************************************************************/
/*
	Designed by: Hongshai.Li
	Build:	06.21.2005
	Modify:
	Discription:The routine is for test FLASH.
*/
/********************************************************************/

#include <stdio.h>
#include <csl.h>
#include <csl_emifa.h>
#include <csl_irq.h>
#include <csl_chip.h>

#include "DEC643.h"
#include "FLASH.h"
/********************************************************************/
/*DEC643 EMIFA configuration*/
	EMIFA_Config DEC643ConfigA ={
		/*
	  	EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK)    |
        EMIFA_FMKS(GBLCTL, EK2HZ, CLK)          |
        EMIFA_FMKS(GBLCTL, EK2EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS)    |
        EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE)     |
        EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ)        |
        EMIFA_FMKS(GBLCTL, EK1EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE)      |
        EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE),
        
        EMIFA_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFA_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, TA, DEFAULT)         |
        EMIFA_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, MTYPE, SDRAM64)      |
        EMIFA_FMKS(CECTL, RDHLD, DEFAULT),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(7))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC8)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(1)),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC8)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, SYNC32)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),
        
        EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS)       |
        EMIFA_FMKS(SDCTL, SDRSZ, 12ROW)        |
        EMIFA_FMKS(SDCTL, SDCSZ, 8COL)         |
        EMIFA_FMKS(SDCTL, RFEN, ENABLE)        |
        EMIFA_FMKS(SDCTL, INIT, YES)           |
        EMIFA_FMKS(SDCTL, TRCD, OF(1))         |
        EMIFA_FMKS(SDCTL, TRP, OF(1))          |
        EMIFA_FMKS(SDCTL, TRC, OF(5))          |
        EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
        
        EMIFA_FMKS(SDTIM, XRFR, OF(0))         |
        EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
        
        EMIFA_FMKS(SDEXT, WR2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, WR2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, WR2WR, OF(1))        |
        EMIFA_FMKS(SDEXT, R2WDQM, OF(3))       |
        EMIFA_FMKS(SDEXT, RD2WR, OF(2))        |
        EMIFA_FMKS(SDEXT, RD2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, RD2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, THZP, OF(2))         |
        EMIFA_FMKS(SDEXT, TWR, OF(2))          |
        EMIFA_FMKS(SDEXT, TRRD, OF(0))         |
        EMIFA_FMKS(SDEXT, TRAS, OF(6))         |
        EMIFA_FMKS(SDEXT, TCL, OF(1)),           
        
        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2)    |
        EMIFA_FMKS(CESEC, RENEN, READ)         |
        EMIFA_FMKS(CESEC, CEEXT, ACTIVE)       |
        EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE)      |
        EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
        */
        0x00052078,
	   0xffffffd3,     
       0x73a28e01,   
       0xffffff07, 
       0x22a28a42,   
       0x57115000, /*sdctl SDRAM control register value*/
	   0x0000081b, /*sdtim SDRAM timing register value*/
	   0x001faf4d, /*sdext SDRAM extension register value*/
	   0x00000002, /*cesec0 CE0 space secondary control register value*/
	   0x00000002, /*cesec1 CE1 space secondary control register value*/
	   0x00000002, /*cesec2 CE2 space secondary control register value*/
	   0x00000073
};
/**************************************************************************/

extern far void vectors();

/* Define source and destination arrays for flash tests */
Uint16 buffer[256];
/**************************************************************************/
void main()
{
	Uint16 i, j, k, page, limit;
    Uint32 startaddr, addr;	
	/* perform all initializations                           */
	/*Initialize CSL */
	CSL_init();

	/* Initialize EMIFA, CE0 is for SDRAM, CE1 is for FLASH memory, 
	  CE2 is for CPLD registers. */
	EMIFA_config(&DEC643ConfigA);
	
	/* Initialize interrupt vector*/
	//Point to the IRQ vector table
    IRQ_setVecs(vectors); 
    IRQ_nmiEnable();
    IRQ_globalEnable();

	/* Test CPLD registers */
	/*
	for(;;)
	{
		DEC643_rset(DEC643_CTL_REG,0x00);
		DEC643_waitusec(1);
		DEC643_rset(DEC643_CTL_REG,0xEF);
	}
	*/
	
	/* Begin testing FLash. */
    /* Program the Flash page by page, 256 words at a time */
        /* Set Flash page. */
        page  = 0;
        for(page = 0;page<8;page++)
        {
	        DEC643_rset(DEC643_FLASH_REG, page);
			DEC643_waitusec(1);
	        /* Erase all of the Flash for each page */
	        DEC643_FLASH_erase(DEC643_FLASH_BASE, DEC643_FLASH_PAGESIZE);
			DEC643_waitusec(1);
        }
		/* Get FLASH base address. */
        addr = DEC643_FLASH_BASE;
                
        for(page = 0;page<8;page++)
        {
	        /* Get FLASH base address. */
        	addr = DEC643_FLASH_BASE;
	        /* Set Flash page*/
       		DEC643_rset(DEC643_FLASH_REG, page);       		 
			DEC643_waitusec(1);
	        limit = 8;
	        for (i = 0; i < limit; i++)
	        {
	            for (j = 0; j < 128; j++)
	            {
	                startaddr = addr;
	                /*每次写入512个字节，以16位的数据为基数*/
	                for (k = 0; k < 256; k++)
	                {
	                    buffer[k] = (addr + i + page) & 0xffff;
	                    addr += 2;
						printf("flash test done!\n");
	                }
	                DEC643_FLASH_write((Uint32)buffer, startaddr, 512);
	            }
	        }
       	 }
	        
    /* Verify the Flash page by page, 512 bytes at a time */
    for (page = 0; page < 8; page++)
    {
        /*取FLASh的首址*/
        addr = DEC643_FLASH_BASE;
        /* Set Flash page */
        DEC643_rset(DEC643_FLASH_REG, page);
        /*等待延时*/
		DEC643_waitusec(1);
        addr = DEC643_FLASH_BASE;
        limit = 8;
        for (i = 0; i < limit; i++)
        {
            for (j = 0; j < 128; j++)
            {
                startaddr = addr;
                DEC643_FLASH_read(startaddr, (Uint32)buffer, 512);
                for (k = 0; k < 256; k++)
                {
                    if (buffer[k] != ((addr + i + page) & 0xffff))
                    {     
                    	printf("Flash test is failure!\n");
                    	exit(0);
                    }
                    addr += 2;
                }
            }
        }
    }
    /*测试完成*/
    printf("Flash test is OK!\n");
}
/**************************************************************************/
/* End of DEC643_FLASH.c 	*/
/*************************************************************************/