include.h

DSP link 测试

/********************************* Start File ***********************************/
#ifndef _include_h_
#define _include_h_

/******************************************************************************/
/*                            INCLUDES:                                       */
/******************************************************************************/
#include "../include_C64x/datatype.h"
#include "../include_C64x/MSG.h"
#include "../include_C64x/REGS.h"
#include "../include_C64x/EMIF.h"
#include "../include_C64x/GPIO.h"
#include "../include_C64x/EDMA.c"
#include "../include_C64x/SPORT.c"
#include "../include_C64x/timer.c"
#include "../include_C64x/ata_msg.h"
/******************************************************************************/
/*                             MACRO:                                         */
/******************************************************************************/
#define RESET_OK	0x11111111
#define DELAYCOUNT	100000           //The time of delay: (us)
#define MASTER_DSP	1
#define SLAVE_ONE   2
#define SLAVE_TWO   3

/*------------------------------------------*/
/*  Define the IMAGE PARAMETERS             */
/*------------------------------------------*/
#define SYMBOLGRAY  	   255
#define ROW       		   16
#define COL		  		   16
#define IMG_SIZE          (ROW*COL)        //Image size in half-word
#define IMG_SIZE_IN_WORD  (IMG_SIZE>>1)    //Image size in word

/*---------------------------------------------*/
/*  Define the Peripheral Address              */
/*---------------------------------------------*/
#define ADDR_OF_DUALPORT_RAM		0x6C000004
#define ADDR_OF_TRANS_TO_DSP1		0x80000000
#define ADDR_OF_REC_FROM_DSP1		0x80000004
#define ADDR_OF_TRANS_TO_DSP2		0x80000008
#define ADDR_OF_REC_FROM_DSP2		0x8000000C
#define ADDR_OF_REC_ATA_MSG			0xA0000110
#define ADDR_OF_TRANS_ATA_MSG		0xA0000000		
//#define ADDR_OF_TRANS_TO_HOTLINK 0xA0000000
#define ADDR_OF_REC_FROM_FIFO		0xB0000000
//#define MUXH                     0x019C0000

/*------------------------------------------*/
/*  Define the EMIF register PARAMETERS     */
/*------------------------------------------*/
#define EMIFA_GCR_PARAMS ((1<<BRMODE)+(1<<HOLD)+(1<<HOLDA)+(1<<CLK6EN)+(1<<EK1EN)+(1<<EK2EN)+(0<<EK2RATE))
#define EMIFA_CE0_PARAMS (4<<MTYPE)
#define EMIFA_CE0SEC_PARAMS ((1<<SNCCLK)+(1<<RENEN)+(1<<CEEXT)+(2<<SYNCRL)+(0<<SYNCWL))
//#define EMIFA_CE2_PARAMS ((1<<WRITESETUP)+(1<<WRITESTROBE)+(0<<WRITEHOLD)+(10<<MTYPE))
#define EMIFA_CE2_PARAMS (10<<MTYPE)			//DPRAM for communication
//#define EMIFA_CE2SEC_PARAMS ((1<<SNCCLK)+(1<<RENEN)+(1<<CEEXT)+(2<<SYNCRL)+(0<<SYNCWL))
#define EMIFA_CE2SEC_PARAMS ((0<<SNCCLK)+(1<<RENEN)+(1<<CEEXT)+(2<<SYNCRL)+(0<<SYNCWL))
#define EMIFA_CE3_PARAMS (4<<MTYPE)
#define EMIFA_CE3SEC_PARAMS ((1<<RENEN)+(0<<CEEXT)+(0<<SYNCRL)+(1<<SNCCLK))

#define EMIFB_GCR_PARAMS ((1<<BRMODE)+(1<<HOLD)+(1<<HOLDA)+(1<<EK1EN)+(1<<EK1HZ))
#define EMIFB_CE0_PARAMS (9<<MTYPE)
#define EMIFB_CE1_PARAMS (0<<MTYPE)
#define EMIFB_CE3_PARAMS ((1<<WRITESETUP)+(1<<WRITESTROBE)+(0<<WRITEHOLD)+(1<<MTYPE))
#define EMIFB_SDCTRL_PARAMS  0x57116000
#define EMIFB_SDRP_PARAMS    0x61a
#define EMIFB_SDEXT_PARAMS   0x54529

/*------------------------------------------*/
/*  Define the EDMA register PARAMETERS     */
/*------------------------------------------*/
#define CHANNEL_OF_REC_FROM_FIFO    8
//#define CHANNEL_OF_TRANS_TO_HOTLINK 9
#define CHANNEL_OF_REC_FROM_DSP1    10
#define CHANNEL_OF_REC_FROM_DSP2    11
#define CHANNEL_OF_TRANS_TO_DSP1    22
#define CHANNEL_OF_TRANS_TO_DSP2    23
#define CHANNEL_OF_TARNS_TO_DPRAM   24
#define CHANNEL_OF_REC_FROM_FIFO_TRASH   25
#define CHANNEL_OF_INTERNAL_EXCH    21
#define FIXED_ADDR_MODE      0
#define INCREMENT_ADDR_MODE  1
#define DECREMENT_ADDR_MODE  2

/*------------------------------------------*/
/*  Define the McBSP register PARAMETERS    */
/*------------------------------------------*/
#define McBSP_TO_DSP1		1
#define McBSP_TO_DSP2		0

/*------------------------------------------*/
/*  Define the GPIO register PARAMETERS     */
/*------------------------------------------*/
#define GPEN_PARAMS  ((1<<GPIO_0)+(1<<GPIO_3)+(1<<GPIO_12)+(1<<GPIO_14))
#define GPDIR_PARAMS ((OUTPUT<<GPIO_0)+(OUTPUT<<GPIO_3)+(OUTPUT<<GPIO_12)+(OUTPUT<<GPIO_14))
#define FIFO_01_HIGH()          SET_BIT(GPVAL,GPIO_0)
#define FIFO_01_LOW()           RESET_BIT(GPVAL,GPIO_0)
#define FIFO_02_HIGH()          SET_BIT(GPVAL,GPIO_3)
#define FIFO_02_LOW()           RESET_BIT(GPVAL,GPIO_3)
#define LED_OFF()               SET_BIT(GPVAL,GPIO_12)
#define LED_ON()                RESET_BIT(GPVAL,GPIO_12)
#define SELECT_FLASH_0()        RESET_BIT(GPVAL,GPIO_14)
#define SELECT_FLASH_1()        SET_BIT(GPVAL,GPIO_14)

/*---------------------------*/
/*  Define the Structures:   */
/*---------------------------*/
typedef enum{
  good = 0,
  normality,
  abnormality,
  bad
}
DSP_STATE_TYPE;

typedef struct
{
  DSP_STATE_TYPE Dsp0State;
  DSP_STATE_TYPE Dsp1State;
  DSP_STATE_TYPE Dsp2State;
}
DSP_STATE;

typedef struct
{
  unsigned int MaxTime;
  unsigned int MinTime;
  unsigned int TotalTime;
  unsigned int AverageTime;
}
TIME_STAT;

/******************************************************************************/
/*                              DECLARATION:                                  */
/******************************************************************************/
void InitDSP(void);
///void proc_msg(void);

#endif
/********************************** End File ************************************/