master_main.c

DSP link 测试

//2007.11.16 by axia
//master DSP program
//dsp0/cpu1

#include <stdio.h>
#include <c6x.h>
#include <math.h>
#include "include.h"
#include "target.h"
#define TEST_SIZE	256
#pragma DATA_SECTION(Buffer_1,"STORE_IN_IRAM");
	INT16U Buffer_1[TEST_SIZE];
#pragma DATA_SECTION(Buffer_2,"STORE_IN_IRAM");
	INT16U Buffer_2[TEST_SIZE];
#pragma DATA_SECTION(Buffer_3,"STORE_IN_IRAM");
	INT8U Buffer_3[TEST_SIZE];   
#pragma DATA_SECTION(Buffer_4,"STORE_IN_IRAM");
	INT16U Buffer_4[TEST_SIZE];
volatile int exch_flag = 0;

extern far void RelocateISTP();
void InitDSP();	

int edma_start_8to16(int src, int dst, unsigned int ch, int sum, int dum, int islink, int size)
{ 
//	EDMA_REG *edma_reg = (EDMA_REG*)EVENT_PARAMS_ADDR(ch); 
	
	if((ch>=EDMA_CHANNEL_NUM)) 
      return 1;

  *(unsigned volatile int *)ECRL |= (1<<ch);		//clear  + (1<<DS)
    
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + OPT) = (EDMA_PRI<<PRI) + (2<<ESIZE)+ (sum<<SUM)
  													+ (1<<TCINT)   + ((ch%16)<<TCC) + ((ch/16)<<TCCM) 
  													+(dum<<DUM) + (islink<<LINK) + (1<<FS);//;//
 
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + SRC) = src;
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + DST) = dst;
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + IDX) = 0x0002+(size<<15);//---0x00020000;// 2;//
   
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + CNT) = 0x00030000+size/4;//(0x00010000+size/2);//---
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + LNK)= ((0xffff& EVENT_PARAMS_ADDR(ch)));//NULL_PARAMS_ADDR)); //0x00020000;//+((size/2)<<16);

  *(unsigned volatile int *)CIERL |= (1<<ch);	//enable channel interrupt
  *(unsigned volatile int *)EERL |= (1<<ch);	//enable EVENT

  return 0;
}

/*
int edma_start_8to16(int src, int dst, unsigned int ch, unsigned char lnkch, int sum, int dum, int islink, int size)
{ 
//	EDMA_REG *edma_reg = (EDMA_REG*)EVENT_PARAMS_ADDR(ch); 
	
	if((ch>=EDMA_CHANNEL_NUM)) 
      return 1;

  *(unsigned volatile int *)ECRL |= (1<<ch);		//clear  + (1<<DS)  

    
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + OPT) = (EDMA_PRI<<PRI) + (2<<ESIZE)+ (sum<<SUM) 
  													+(dum<<DUM) + (islink<<LINK) + (1<<FS);// 
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + SRC) = src;
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + DST) = dst;
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + IDX) = 0x00000002; //;(size<<15);//---0x00020000;// 
   
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + CNT) = (size>>1);//---
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + LNK)= ((0xffff & EVENT_PARAMS_ADDR(lnkch))); //0x00020000;//+((size/2)<<16);

  *(unsigned volatile int *)CIERL |= (1<<ch);	//enable channel interrupt
  *(unsigned volatile int *)EERL |= (1<<ch);	//enable EVENT
//////////////////////////////
//  *(unsigned volatile int *)ECRH |= (1<<(lnkch-32));		//clear  + (1<<DS)
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(lnkch) + OPT) = (EDMA_PRI<<PRI) + (2<<ESIZE)+ (sum<<SUM) 
  													 + (1<<TCINT)   + ((ch%16)<<TCC) + ((ch/16)<<TCCM)
  													+(dum<<DUM) + (islink<<LINK) + (1<<FS);//;//
 
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(lnkch) + SRC) = (src+size>>1);
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(lnkch) + DST) = (dst+size);
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(lnkch) + IDX) = 0x00000002; //;(size<<15);//---0x00020000;// 
   
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(lnkch) + CNT) = (size>>2);//---
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(lnkch) + LNK)= ((0xffff & NULL_PARAMS_ADDR)); //0x00020000;//+((size/2)<<16);

//  *(unsigned volatile int *)CIERH |= (1<<(lnkch-32));	//enable channel interrupt
//  *(unsigned volatile int *)EERH |= (1<<(lnkch-32));	//enable EVENT

  return 0;
}
*/
volatile int interrupt_cnt = 0;
void main()
{
	int i = 0, error = 0, set_i = 0;
	InitDSP();
	
	while(1)//main loop
	{
		error = 0;
		set_i = 0;
		for(i = 0; i < TEST_SIZE;i++)
		{
			Buffer_1[i] = 0;
			Buffer_1[i+TEST_SIZE] = 0;
			Buffer_2[i] = 0;
			Buffer_3[i] = i;
			Buffer_4[i] = 0;
		}
		edma_start_8to16((int)Buffer_3, (int)Buffer_1, CHANNEL_OF_INTERNAL_EXCH, 
						INCREMENT_ADDR_MODE, 3, 1, TEST_SIZE);
		while(exch_flag ==0 )
{
		SET_BIT(ESRL, CHANNEL_OF_INTERNAL_EXCH);
		delay_msec(1,100);
		set_i++;
						
}
		printf("set_i: %d\n",set_i);
		printf("interrupt_cnt: %d\n",interrupt_cnt);
		while(exch_flag ==0 );
		exch_flag = 0;
		
		for(i= 0;i < TEST_SIZE; i++)
			if(Buffer_3[i] != Buffer_1[i])
			{
				printf("%d\tand\t%d\n", Buffer_3[i],Buffer_1[i]);	
				error++;
			}
		printf("error: %d\n", error);
	}
}

void InitDSP()
{
	volatile int temp, i;
  
	// Initial the common control registers 
	CSR = (1<<EN);        //enable the little endian mode
	IER = (1<<NMIE);
	ICR = 0xffff;         //clear the all interruptions
	RelocateISTP();
  
	// Initial the EMIFA and EMIFB register
	*(volatile unsigned int *)EMIFA_GCR = EMIFA_GCR_PARAMS;			//EMIFA global control
	*(volatile unsigned int *)EMIFA_CE0 = EMIFA_CE0_PARAMS;			//32bit programmable sync for DSPs，与其他DSP数据通讯
	*(volatile unsigned int *)EMIFA_CE0SEC = EMIFA_CE0SEC_PARAMS;
	*(volatile unsigned int *)EMIFA_CE2 = EMIFA_CE2_PARAMS;			//通讯双口RAM
	*(volatile unsigned int *)EMIFA_CE2SEC = EMIFA_CE2SEC_PARAMS;
	*(volatile unsigned int *)EMIFA_CE3 = EMIFA_CE3_PARAMS;			//32bit programmable sync for FIFO，收图
	*(volatile unsigned int *)EMIFA_CE3SEC = EMIFA_CE3SEC_PARAMS;	// FWFT mode
   
	*(volatile unsigned int *)EMIFB_GCR = EMIFB_GCR_PARAMS;		//EMIFB global control
	*(volatile unsigned int *)EMIFB_CE0 = EMIFB_CE0_PARAMS;		//16bit sync for SDRAM
	*(volatile unsigned int *)EMIFB_CE1 |= EMIFB_CE1_PARAMS;	//8bit async for FLASH
	*(volatile unsigned int *)EMIFB_CE3 = EMIFB_CE3_PARAMS;		//16bit async for dual-RAM，显示图像
	*(volatile unsigned int *)EMIFB_SDCTRL = EMIFB_SDCTRL_PARAMS;
	*(volatile unsigned int *)EMIFB_SDRP = EMIFB_SDRP_PARAMS;
	*(volatile unsigned int *)EMIFB_SDEXT = EMIFB_SDEXT_PARAMS;
  
	//Initial the GPIO register
	*(volatile unsigned int *)GPEN |= GPEN_PARAMS;
	*(volatile unsigned int *)GPDIR = GPDIR_PARAMS;
	FIFO_01_LOW();
	FIFO_02_LOW();

	//Initial the EDMA registers
	REG_WRITE(CIERL, 0x0);
	REG_WRITE(CIERH, 0x0);
	REG_WRITE(CIPRL, 0xFFFF);
	REG_WRITE(CIPRH, 0xFFFF);
  
	REG_WRITE(EERL, 0x0);
	REG_WRITE(EERH, 0x0);
	REG_WRITE(ECRL, 0xFFFF);
	REG_WRITE(ECRH, 0xFFFF);
  
	edma_null_init();
             
/*
	*(unsigned volatile int *)QDMA_OPT = (QDMA_PRI<<PRI) + (1<<SUM) + (1<<DUM) + (1<<TCINT) 
										+ (CHANNEL_OF_TARNS_TO_DPRAM%16<<TCC)
										+ (CHANNEL_OF_TARNS_TO_DPRAM/16<<TCCM) + (1<<FS);
	*(unsigned volatile int *)QDMA_SRC = (int)img_buff;
	*(unsigned volatile int *)QDMA_DST = ADDR_OF_DUALPORT_RAM;
	*(unsigned volatile int *)QDMA_CNT = IMG_SIZE_IN_WORD;	
	*(unsigned volatile int *)CIERL |= (1<<CHANNEL_OF_TARNS_TO_DPRAM);
*/
	
	
	//Open the needed Interrupt，打开需要使用的
	ICR = IFR | ((1<<IF6)+(1<<IF8));
	IER |= ((1<<IF6)+(1<<IF8));
	CSR |= (1<<GIE);	
}

//从红外头收图中断
interrupt void RecOrg_isr()
{
}

//从DSP超时无响应中断
interrupt void timer1_isr()
{
}

//EDMA中断
interrupt void edma_isr()
{
	if(GET_BIT(CIPRL,CHANNEL_OF_INTERNAL_EXCH))
	{
		REG_WRITE(CIPRL,1<<CHANNEL_OF_INTERNAL_EXCH);
		exch_flag = 1;
		interrupt_cnt++;
	}
}
/*
//////one frame OK
int edma_start_8to16(int src, int dst, unsigned int ch, int sum, int dum, int islink, int size)
{ 
//	EDMA_REG *edma_reg = (EDMA_REG*)EVENT_PARAMS_ADDR(ch); 
	
	if((ch>=EDMA_CHANNEL_NUM)) 
      return 1;

  *(unsigned volatile int *)ECRL |= (1<<ch);		//clear  + (1<<DS)
    
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + OPT) = (EDMA_PRI<<PRI) + (2<<ESIZE)+ (sum<<SUM)
  													+ (1<<TCINT)   + ((ch%16)<<TCC) + ((ch/16)<<TCCM) 
  													+(dum<<DUM) + (islink<<LINK) + (1<<FS);//;//
 
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + SRC) = src;
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + DST) = dst;
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + IDX) = 2;//0x0002+(size<<15);//---0x00020000;// 
   
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + CNT) = size;//(0x00010000+size/2);//---
  *(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + LNK)= ((0xffff& NULL_PARAMS_ADDR)); //0x00020000;//+((size/2)<<16);

  *(unsigned volatile int *)CIERL |= (1<<ch);	//enable channel interrupt
  *(unsigned volatile int *)EERL |= (1<<ch);	//enable EVENT

  return 0;
}
*/