📄 sport.h
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/******************************************************************************/
/* SPORT.H - TMS320C64 Peripheral Support Library SPORTS Support */
/******************************************************************************/
/*msg pingpong mechanism version
data: 2003/10
*/
#ifndef _SPORT_H_
#define _SPORT_H_
#ifndef _EDMA_H_
#include "EDMA.h"
#endif
#ifndef _MSG_H_
#include "msg.h"
#endif
#define _PINGPONG_VER
#define MSG_SIZE (sizeof(MSG)/4) //element num per frame
#define ELEMENT_SIZE 32 //element size in bit
#define SPORT_ClkGdv 1 //75M
#define McBSP_CHANNEL_NUM 3
#define SPI_TRANS_PARAMS_RELOAD 0x01A00600
#define SPI_REC_PARAMS_RELOAD 0x01A00618
/*
#define TIMER_BASE_ADDR 0x01940000
#define TIMER_CTRL_ADDR(chan) \
(TIMER_BASE_ADDR + ((chan) * 0x40000))
*/
#define McBSP_BASE_A 0x18c0000
#define McBSP_DRR(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000))
#define McBSP_DXR(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 1*4)
#define McBSP_SPCR(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 2*4)
#define McBSP_RCR(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 3*4)
#define McBSP_XCR(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 4*4)
#define McBSP_SRGR(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 5*4)
#define McBSP_MCR(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 6*4)
#define McBSP_RCERE0(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 7*4)
#define McBSP_XCERE0(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 8*4)
#define McBSP_PCR(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 9*4)
#define McBSP_RCERE1(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 10*4)
#define McBSP_XCERE1(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 11*4)
#define McBSP_RCERE2(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 12*4)
#define McBSP_XCERE2(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 13*4)
#define McBSP_RCERE3(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 14*4)
#define McBSP_XCERE3(chan) \
(McBSP_BASE_A + ((chan>>1) * 0x100000) + ((chan) * 0x40000) + 15*4)
#define SP0_MEM_ADDR 0x30000004
#define SP1_MEM_ADDR 0x34000004
#define SP2_MEM_ADDR 0x38000004
#define McBSP_BASE_ADDR(chan) \
(0x18c0000 + ((chan>>1) * 0x100000) + ((chan) * 0x40000))
#define SP_BASE_MEM_ADDR 0x30000000
#define SP_MEM_ADDR(chan) \
(SP_BASE_MEM_ADDR + ((chan) * 0x4000000) + 4)
#define SPORT0_EDMA_R_PING 26
#define SPORT0_EDMA_R_PONG 27
#define SPORT1_EDMA_R_PING 28
#define SPORT1_EDMA_R_PONG 29
#define SPORT2_EDMA_R_PING 30
#define SPORT2_EDMA_R_PONG 31
/*McBSP reg struct*/
typedef struct
{
unsigned int
DRR,
DXR,
SPCR,
RCR,
XCR,
SRGR,
MCR,
RCERE0,
XCERE0,
PCR,
RCERE1,
XCERE1,
RCERE2,
XCERE2,
RCERE3,
XCERE3;
}McBSP_REG;
/* Control Register Bitfield */
/* SPCR */
#define RRST 0 /* Receiver reset */
#define RRDY 1 /* Receiver ready */
#define RFULL 2 /* RSR full error condition */
#define RSYNCERR 3 /* Receive synchronization error */
#define RINTM 4 /* Receive interrupt mode */
#define DXENA 7 /* DX Enabler */
#define CLKSTP 11 /* Clock stop mode */
#define RJUST 13 /* Receive data sign-extension and justification mode */
#define DLB 15 /* Digital loopback mode */
#define XRST 16 /* Transmitter reset */
#define XRDY 17 /* Transmitter ready */
#define XEMPTY 18 /* Transmit shift register (XSR) empty */
#define XSYNCERR 19 /* Transmit synchronization error */
#define XINTM 20 /* Transmit interrupt mode */
#define GRST 22 /* Sample rate generator reset */
#define FRST 23 /* Frame sync generator reset */
#define SOFT 24 /* Serial clock emulation mode */
#define FREE 25 /* Serial clock free running mode */
/* SRGR */
#define GSYNC 31 /* Sample rate generator clock synchronization */
#define CLKSP 30 /* CLKS polarity clock edge select */
#define CLKSM 29 /* McBSP sample rate generator clock mode */
#define FSGM 28 /* SRG transmit frame synchronization mode */
#define FPER 16 /* Frame period */
#define FWID 8 /* Frame width */
#define CLKGDV 0 /* Sample rate generator clock divider */
/* RCR/XCR */
#define WDREVRS 4 /* Receive/Transmit 32-bit bit reversal feature */
#define WDLEN1 5 /* Receive/Transmit element length in phase 1 */
#define FRLEN1 8 /* Receive/Transmit frame length in phase 1 */
#define DATDLY 16 /* Receive/Transmit data delay */
#define FIG 18 /* Receive/Transmit frame ignore */
#define COMPAND 19 /* Receive/Transmit companding mode */
#define WDLEN2 21 /* Receive/Transmit element length in phase 2 */
#define FRLEN2 24 /* Receive/Transmit frame length in phase 2 */
#define PHASE 31 /* Receive/Transmit phases */
/* PCR */
#define CLKRP 0 /* Receive clock polarity */
#define CLKXP 1 /* Transmit clock polarity */
#define FSRP 2 /* Receive frame synchronization polarity */
#define FSXP 3 /* Transmit frame synchronization polarity */
#define DR_STAT 4 /* DR pin status */
#define DX_STAT 5 /* DX pin status */
#define CLKS_STAT 6 /* CLKS pin status */
#define CLKRM 8 /* Receiver clock mode */
#define CLKXM 9 /* Transmitter clock mode */
#define FSRM 10 /* Receive frame synchronization mode */
#define FSXM 11 /* Transmit frame synchronization mode */
#define RIOEN 12 /* Receiver in general-purpose I/O mode only when /RRST = 0 in SPCR*/
#define XIOEN 13 /* Transmitter in general-purpose I/O mode only when /XRST = 0 in SPCR*/
/* Multichannel Control Register (MCR) */
#define RMCM 0 /* Receive multichannel selection enable */
#define RCBLK 2 /* Receive current subframe */
#define RPABLK 5 /* Receive partition A subframe */
#define RPBBLK 7 /* Receive partition B subframe */
#define RMCME 9 /* Enhanced receive multichannel selection enable (C64x only) RMCME operates in conjunction with XMCME*/
#define XMCM 16 /* Transmit multichannel selection enable*/
#define XCBLK 18 /* Transmit current subframe */
#define XPABLK 21 /* Transmit partition A subframe */
#define XPBBLK 23 /* Transmit partition B subframe */
#define XMCME 25 /* Enhanced transmit multichannel selection enable (C64x only)*/
#define MCBSP_AVAILABLE(chan) \
(GET_BIT(McBSP_SPCR(chan),XEMPTY) ? 0 : 1)
//XEMPTY = 0: XSR is empty.
#define MCBSP_XPIN_ENABLE_VAL ((1<<FSXM) + (1<<CLKXM)+(0<<FSRM) + (0<<CLKRM))
#define MCBSP_XPIN_DISABLE_VAL ((0<<FSXM) + (0<<CLKXM)+(0<<FSRM) + (0<<CLKRM))
#define MCBSP_X_PIN_DISABLE(chan) \
(REG_WRITE(McBSP_PCR(chan), MCBSP_XPIN_DISABLE_VAL))
#define MCBSP_X_PIN_ENABLE(chan) \
(REG_WRITE(McBSP_PCR(chan), MCBSP_XPIN_ENABLE_VAL))
/*----------------------------------------------------------------------------*/
/* FUNCTIONS */
/*----------------------------------------------------------------------------*/
int mcbsp_test(unsigned int ch);
void mcbsp_write(int out_data,unsigned int ch);
int mcbsp_read(unsigned int ch);
void mcbsp_init(unsigned int ch, unsigned int ClkGdv);
void mcbsp_test_init(unsigned int ch);
void SPI_Slave_Init(unsigned int ch);
void McBSP_Start(unsigned int ch);
void McBSP_Reset(unsigned int ch);
int SPI_check_sum(int *mem, unsigned int size);
void evt_edmax_init(int src, int dst, int size, int ch);
void evt_edmar_init(int src, int dst, int size, int ch);
int SPORT_edmax_init(int src, unsigned int MsBSP_ch, int size);
int SPORT_edmar_init(int dst, unsigned int MsBSP_ch, int size);
#ifdef _PINGPONG_VER
void SPORT_edmar_ping_pong(int dst_ping, int dst_pong,
unsigned int MsBSP_ch, int size);
int SPORT_edmar_pingpong_init(int dst,int dst_ping,
int dst_pong, unsigned int MsBSP_ch, int size);
#endif
#endif /* ifndef _SPORT_H_ */
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