protect.lst
来自「为aduc7026应用开发例程」· LST 代码 · 共 750 行 · 第 1/3 页
LST
750 行
43: ERROR = 0;
0000001A 2100 MOV R1,#0x0
0000001C 4800 LDR R0,=ERROR ; ERROR
0000001E 7001 STRB R1,[R0,#0x0] ; ERROR
45: POWKEY1 = 0x01;
00000020 2101 MOV R1,#0x1
00000022 4800 LDR R0,=0xFFFF0404
00000024 6001 STR R1,[R0,#0x0]
46: POWCON = 0x00; // 41.78MHz
00000026 2100 MOV R1,#0x0
00000028 4800 LDR R0,=0xFFFF0408
0000002A 6001 STR R1,[R0,#0x0]
47: POWKEY2 = 0xF4;
ARM COMPILER V2.42, protect 19/06/07 11:55:41 PAGE 5
0000002C 22F4 MOV R2,#0xF4
0000002E 4800 LDR R0,=0xFFFF040C
00000030 6002 STR R2,[R0,#0x0]
49: GP1CON = 0x011; // Setup tx & rx pins on P1.0 and P1.1
00000032 2211 MOV R2,#0x11
00000034 4800 LDR R0,=0xFFFFF404
00000036 6002 STR R2,[R0,#0x0]
52: COMCON0 = 0x80; // Setting DLAB
00000038 2280 MOV R2,#0x80
0000003A 4800 LDR R0,=0xFFFF070C
0000003C 6002 STR R2,[R0,#0x0]
53: COMDIV0 = 0x88; // updated for rev H
0000003E 2288 MOV R2,#0x88
00000040 4800 LDR R0,=0xFFFF0700
00000042 6002 STR R2,[R0,#0x0]
54: COMDIV1 = 0x00;
00000044 4800 LDR R0,=0xFFFF0704
00000046 6001 STR R1,[R0,#0x0]
55: COMCON0 = 0x07; // Clearing DLAB
00000048 2107 MOV R1,#0x7
0000004A 4800 LDR R0,=0xFFFF070C
0000004C 6001 STR R1,[R0,#0x0]
57: GP4DAT = 0x04000000; // configure P4.2 as output
0000004E 4800 LDR R1,=0x4000000
00000050 4800 LDR R0,=0xFFFFF460
00000052 6001 STR R1,[R0,#0x0]
58: FEEMOD = 0x8; // bit 3 should be set to allow erase/write command
00000054 2108 MOV R1,#0x8
00000056 4800 LDR R0,=0xFFFFF804
00000058 6001 STR R1,[R0,#0x0]
62: erase_page(0xF000); // erase page 120-123
0000005A 4800 LDR R0,=0xF000
0000005C F7FF BL erase_page?T ; T=0x0001 (1)
0000005E FFD0 BL erase_page?T ; T=0x0001 (2)
64: for (i=0;i<10;i++) {
00000060 2400 MOV R4,#0x0
00000062 L_5:
65: count ++; // save numbers
00000062 3501 ADD R5,#0x1
00000064 062D LSL R5,R5,#0x18
00000066 0E2D LSR R5,R5,#0x18
66: save(0xF000+2*i, count);
00000068 1C20 MOV R0,R4 ; i
0000006A 0040 LSL R0,R0,#0x1 ; i
0000006C 4800 LDR R1,=0xF000
0000006E 1840 ADD R0,R1
00000070 1C29 MOV R1,R5 ; count
00000072 0609 LSL R1,R1,#0x18 ; count
00000074 0E09 LSR R1,R1,#0x18
00000076 F7FF BL save?T ; T=0x0001 (1)
00000078 FFC3 BL save?T ; T=0x0001 (2)
67: }
0000007A 3401 ADD R4,#0x1
0000007C 1C20 MOV R0,R4 ; i
0000007E 280A CMP R0,#0xA ; i
00000080 D3EF BCC L_5 ; T=0x00000062
69: for (i=0;i<10;i++){ // Output Data
00000082 2400 MOV R4,#0x0
00000084 L_10:
70: senddata (load(0xF000+2*i));
00000084 1C20 MOV R0,R4 ; i
00000086 0040 LSL R0,R0,#0x1 ; i
00000088 4800 LDR R1,=0xF000
0000008A 1840 ADD R0,R1
0000008C F7FF BL load?T ; T=0x0001 (1)
0000008E FFB8 BL load?T ; T=0x0001 (2)
ARM COMPILER V2.42, protect 19/06/07 11:55:41 PAGE 6
00000090 0400 LSL R0,R0,#0x10 ; load?T
00000092 0C00 LSR R0,R0,#0x10
00000094 F7FF BL senddata?T ; T=0x0001 (1)
00000096 FFB4 BL senddata?T ; T=0x0001 (2)
71: }
00000098 3401 ADD R4,#0x1
0000009A 1C20 MOV R0,R4 ; i
0000009C 280A CMP R0,#0xA ; i
0000009E D3F1 BCC L_10 ; T=0x00000084
73: protect_page(0xBFFFFFFF); // protect pages 120-123
000000A0 4800 LDR R0,=0xBFFFFFFF
000000A2 F7FF BL protect_page?T ; T=0x0001 (1)
000000A4 FFAD BL protect_page?T ; T=0x0001 (2)
74: RSTSTA = 0x02; // software reset
000000A6 2102 MOV R1,#0x2
000000A8 4800 LDR R0,=0xFFFF0230
000000AA 6001 STR R1,[R0,#0x0]
103: return 0;
000000AC 2000 MOV R0,#0x0
000000AE ; SCOPE-END
104: }
000000AE B002 ADD R13,#0x8
000000B0 BC08 POP {R3}
000000B2 4718 BX R3
000000B4 ENDP ; 'main'
*** CODE SEGMENT '?PR?delay?T?protect':
106: void delay (int length) { // delay
00000000 ---- Variable 'length' assigned to Register 'R0' ----
107: while (length >= 0)
00000000 E000 B L_30 ; T=0x00000004
00000002 L_32:
00000002 3801 SUB R0,#0x1
00000004 L_30:
00000004 1C01 MOV R1,R0 ; length
00000006 2900 CMP R1,#0x0 ; length
00000008 DAFB BGE L_32 ; T=0x00000002
109: }
0000000A 4770 BX R14
0000000C ENDP ; 'delay?T'
*** CODE SEGMENT '?PR?protect_page?T?protect':
111: void protect_page(unsigned int addr){
00000000 ---- Variable 'addr' assigned to Register 'R0' ----
112: FEEADR = 0x1234; // Key
00000000 4800 LDR R2,=0x1234
00000002 4800 LDR R1,=0xFFFFF810
00000004 600A STR R2,[R1,#0x0]
113: FEEDAT = 0xA5A5; // Key
00000006 4800 LDR R2,=0xA5A5
00000008 4800 LDR R1,=0xFFFFF80C
0000000A 600A STR R2,[R1,#0x0]
114: FEEPRO = addr;
0000000C 1C01 MOV R1,R0 ; addr
0000000E 4800 LDR R0,=0xFFFFF81C
00000010 6001 STR R1,[R0,#0x0]
115: FEEMOD = 0x48;
00000012 2148 MOV R1,#0x48
00000014 4800 LDR R0,=0xFFFFF804
00000016 6001 STR R1,[R0,#0x0]
116: FEECON = 0x0C;
00000018 210C MOV R1,#0xC
0000001A 4800 LDR R0,=0xFFFFF808
0000001C 6001 STR R1,[R0,#0x0]
117: status = FEESTA&0x03;
0000001E 4800 LDR R0,=0xFFFFF800
00000020 6801 LDR R1,[R0,#0x0]
00000022 2003 MOV R0,#0x3
ARM COMPILER V2.42, protect 19/06/07 11:55:41 PAGE 7
00000024 4001 AND R1,R0
00000026 0609 LSL R1,R1,#0x18
00000028 0E09 LSR R1,R1,#0x18
0000002A 4800 LDR R0,=status ; status
0000002C 7001 STRB R1,[R0,#0x0] ; status
118: while (!(status)) status = FEESTA&0x03;
0000002E E007 B L_34 ; T=0x00000040
00000030 L_36:
00000030 4800 LDR R0,=0xFFFFF800
00000032 6801 LDR R1,[R0,#0x0]
00000034 2003 MOV R0,#0x3
00000036 4001 AND R1,R0
00000038 0609 LSL R1,R1,#0x18
0000003A 0E09 LSR R1,R1,#0x18
0000003C 4800 LDR R0,=status ; status
0000003E 7001 STRB R1,[R0,#0x0] ; status
00000040 L_34:
00000040 4800 LDR R0,=status ; status
00000042 7800 LDRB R0,[R0,#0x0] ; status
00000044 1C01 MOV R1,R0
00000046 2900 CMP R1,#0x0
00000048 D0F2 BEQ L_36 ; T=0x00000030
119: if ((status&0x02)==0x02) ERROR = 1;
0000004A 2102 MOV R1,#0x2
0000004C 4208 TST R0,R1
0000004E D002 BEQ L_38 ; T=0x00000056
00000050 2101 MOV R1,#0x1
00000052 4800 LDR R0,=ERROR ; ERROR
00000054 7001 STRB R1,[R0,#0x0] ; ERROR
00000056 L_38:
121: }
00000056 4770 BX R14
00000058 ENDP ; 'protect_page?T'
*** CODE SEGMENT '?PR?load?T?protect':
124: unsigned short load(unsigned short int addr){
00000000 1C01 MOV R1,R0 ; addr
00000002 ---- Variable 'addr' assigned to Register 'R1' ----
125: FEEADR = addr;
00000002 1C08 MOV R0,R1 ; addr
00000004 0401 LSL R1,R0,#0x10 ; addr
00000006 0C09 LSR R1,R1,#0x10
00000008 4800 LDR R0,=0xFFFFF810
0000000A 6001 STR R1,[R0,#0x0]
126: FEECON = 0x01; // single read command
0000000C 2101 MOV R1,#0x1
0000000E 4800 LDR R0,=0xFFFFF808
00000010 6001 STR R1,[R0,#0x0]
127: status = FEESTA&0x03;
00000012 4800 LDR R0,=0xFFFFF800
00000014 6801 LDR R1,[R0,#0x0]
00000016 2003 MOV R0,#0x3
00000018 4001 AND R1,R0
0000001A 0609 LSL R1,R1,#0x18
0000001C 0E09 LSR R1,R1,#0x18
0000001E 4800 LDR R0,=status ; status
00000020 7001 STRB R1,[R0,#0x0] ; status
128: while (!(status)) status = FEESTA&0x03;
00000022 E007 B L_40 ; T=0x00000034
00000024 L_42:
00000024 4800 LDR R0,=0xFFFFF800
00000026 6801 LDR R1,[R0,#0x0]
00000028 2003 MOV R0,#0x3
0000002A 4001 AND R1,R0
0000002C 0609 LSL R1,R1,#0x18
0000002E 0E09 LSR R1,R1,#0x18
00000030 4800 LDR R0,=status ; status
ARM COMPILER V2.42, protect 19/06/07 11:55:41 PAGE 8
00000032 7001 STRB R1,[R0,#0x0] ; status
00000034 L_40:
00000034 4800 LDR R0,=status ; status
00000036 7800 LDRB R0,[R0,#0x0] ; status
00000038 1C01 MOV R1,R0
0000003A 2900 CMP R1,#0x0
0000003C D0F2 BEQ L_42 ; T=0x00000024
129: if ((status&0x02)==0x02) ERROR = 1;
0000003E 2102 MOV R1,#0x2
00000040 4208 TST R0,R1
00000042 D002 BEQ L_44 ; T=0x0000004A
00000044 2101 MOV R1,#0x1
00000046 4800 LDR R0,=ERROR ; ERROR
00000048 7001 STRB R1,[R0,#0x0] ; ERROR
0000004A L_44:
130: return (FEEDAT);
0000004A 4800 LDR R0,=0xFFFFF80C
0000004C 6800 LDR R0,[R0,#0x0]
131: }
0000004E 4770 BX R14
00000050 ENDP ; 'load?T'
*** CODE SEGMENT '?PR?save?T?protect':
134: void save(unsigned short int addr, unsigned char data){
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