mupsource.vhd

用xilinx写的vhdl乘法器。是二进制的两位乘法器。里面含有代码和电路图。

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:56:31 12/14/2008 
-- Design Name: 
-- Module Name:    MUPSOURCE - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUPSOURCE is
    Port ( A0 : in  STD_LOGIC;
           A1 : in  STD_LOGIC;
           B0 : in  STD_LOGIC;
           B1 : in  STD_LOGIC;
           C5 : out  STD_LOGIC;
           S4 : out  STD_LOGIC;
           S3 : out  STD_LOGIC;
           S2 : out  STD_LOGIC);
end MUPSOURCE;

architecture Behavioral of MUPSOURCE is


component and2 is
port (I1,I2: IN STD_LOGIC; o: out STD_LOGIC);
end component and2;

component or3 is 
port (I1,I2: IN STD_LOGIC; o: out STD_LOGIC);
end component or3;

component not1  is 
port (I1: IN STD_LOGIC; o: out STD_LOGIC);
end component not1;

component HADD1 is 
port (I1,I2:IN STD_LOGIC; X,Z:out STD_LOGIC);
end component HADD1;

component ADD1 is
port (X,Y,Z:IN STD_LOGIC; A,B:out STD_LOGIC);
end component ADD1;
signal p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18:STD_LOGIC;
 
begin
G1: or3  port map(B0,B1,p1);
G2: and2 port map(A0,p1,p2);
G3: and2 port map(B1,A0,p4);
G4: HADD1 port map(p2,p4,p3,p5);
G5: and2 port map(B1,A1,p6);
G6: ADD1 port map(p5,p6,p2,p9,p10);
G7: and2 port map(B0,B1,p1);
G8: and2 port map(p11,A0,p12);
G9: HADD1 port map(p3,p12,S2,p14);
G10: ADD1 port map(p9,p14,p12,S3,p18);
G11: HADD1 port map(p10,p18,C5,S4);
	  
end architecture Behavioral;

entity and2 is 
port (I1,I2:IN STD_LOGIC;o out STD_LOGIC );
end and2;

architecture Behavioral of and2 is
begin 
o <= I1 and2 I2;
end architecture Behavioral;

entity OR3 is 
port (I1,I2:IN STD_LOGIC; o out STD_LOGIC);
end or3;

architecture Behavioral of or3 is 
begin 
0 <= I1 or I2;
end architecture Behavioral;

entity not1 is 
port (I1:IN STD_LOGIC;o out STD_LOGIC );
end not1;

architecture Behavioral of not1 is 
0 <= not I1;
end architecture Behavioral;

entity HADD1 is 
port (Ai,Bi:In STD_LOGIC;Si,Ci out STD_LOGIC);
end HADD1;

Architecture Behavioral of HADD1 is 
component and2 is
port (I1,I2: IN STD_LOGIC; o: out STD_LOGIC);
end component and2;

component or3 is 
port (I1,I2: IN STD_LOGIC; o: out STD_LOGIC);
end component or3;

component not1 is 
port (I1: IN STD_LOGIC; o: ou STD_LOGIC);
end component not1;

signal p1,p2,p3,p4,p5 : STD_LOGIC;
begin 
G1: not1 port map(Bi,p1);
G2: and2 port map(Ai,p2,p1);
G3: not1 port map(Ai,p3);
G4: and2 port map(p3,Bi,p5);
G5: and2 port map(Ai,Bi,Ci);
G6: or3  port map(p1,p5,Si);
end architecture Behavioral;

entity ADD1 is 
port (Ai,Bi,Ci:in STD_LOGIC;Cj,Si:out STD_LOGIC);
end ADD1;

Architecture Behavioral of ADD1 is 
component and2 is
port (I1,I2: IN STD_LOGIC; o: out STD_LOGIC);
end component and2;

component or3 is 
port (I1,I2: IN STD_LOGIC; o: out STD_LOGIC);
end component or3;

component not1 is 
port (I1: IN STD_LOGIC; o: ou STD_LOGIC);
end component not1;
signal p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11;
G1: and2 port map(Ai,Bi,p1);
G2: not1 port map(Bi,p3);
G3: and2 port map(Ai,p3,p2);
G4: not1 port map(Ai,p4);
G5: and2 port map(Bi,p4,p5);
G6: or3  port map(p2,p5,p6);
G7: and2 port map(p6,Ci,p7);
G8: or3  port map(p7,p1,Cj);
G9: not1 port map(Ci,p9);
G10:and2 port map(p6,p9,p8);
G11:not1 port map(p6,p10);
G12:and2 port map(p10,Ci,p11);
C13:or3  port map(p11,p8,,Si);
end architecture Behavioral;