mcf51xx_reg.h

freescale badge board 开发板测试 源程序

#define MCF_SCIC3_REG(portno)  (*(hcc_reg8*)(&_IPSBAR[0x3E+(portno*8)]))
#define MCF_SCID_REG(portno)	 (*(hcc_reg8*)(&_IPSBAR[0x3F+(portno*8)]))	
#define MCF_SCIBD_REG(portno)  (*(hcc_reg16*)(&_IPSBAR[0x38+(portno*8)]))

#if  (SCI_NO==0)
#define MCF_SCIBDH              MCF_SCI1BDH_REG
#define MCF_SCIBDL              MCF_SCI1BDL_REG
#define MCF_SCIC1               MCF_SCI1C1_REG
#define MCF_SCIC2               MCF_SCI1C2_REG
#define MCF_SCIS1               MCF_SCI1S1_REG
#define MCF_SCIS2               MCF_SCI1S2_REG
#define MCF_SCID                MCF_SCI1D_REG
#define MCF_SCIBD               MCF_SCI1BD_REG
#else
#define MCF_SCIBDH              MCF_SCI2BDH_REG
#define MCF_SCIBDL              MCF_SCI2BDL_REG
#define MCF_SCIC1               MCF_SCI2C1_REG
#define MCF_SCIC2               MCF_SCI2C2_REG
#define MCF_SCIS1               MCF_SCI2S1_REG
#define MCF_SCIS2               MCF_SCI2S2_REG
#define MCF_SCID                MCF_SCI2D_REG
#define MCF_SCIBD               MCF_SCI2BD_REG
#endif

/* Bit definition for SCIBDH register */
#define MCF_SCIBDH_REG_LBKDIE_BIT   (1<<7)
#define MCF_SCIBDH_REG_RXEDGIE_BIT  (1<<6)

/* Bit definition for SCIC1 register */
#define MCF_SCIC1_REG_LOOPS_BIT     (1<<7)
#define MCF_SCIC1_REG_SCISWAI_BIT   (1<<6)
#define MCF_SCIC1_REG_RSRC_BIT      (1<<5)
#define MCF_SCIC1_REG_M_BIT         (1<<4)
#define MCF_SCIC1_REG_WAKE_BIT      (1<<3)
#define MCF_SCIC1_REG_ILT_BIT       (1<<2)
#define MCF_SCIC1_REG_PE_BIT        (1<<1)
#define MCF_SCIC1_REG_PT_BIT        (1<<0)

/* Bit definition for SCIC2 register */
#define MCF_SCIC2_REG_TIE_BIT       (1<<7)
#define MCF_SCIC2_REG_TCIE_BIT      (1<<6)
#define MCF_SCIC2_REG_RIE_BIT       (1<<5)
#define MCF_SCIC2_REG_ILIE_BIT      (1<<4)
#define MCF_SCIC2_REG_TE_BIT        (1<<3)
#define MCF_SCIC2_REG_RE_BIT        (1<<2)
#define MCF_SCIC2_REG_RWU_BIT       (1<<1)
#define MCF_SCIC2_REG_SBK_BIT       (1<<0)

/* Bit definition for SCIC3 register */
#define MCF_SCIC3_REG_R8_BIT        (1<<7)
#define MCF_SCIC3_REG_T8_BIT        (1<<6)
#define MCF_SCIC3_REG_TXDIR_BIT     (1<<5)
#define MCF_SCIC3_REG_TXINV_BIT     (1<<4)
#define MCF_SCIC3_REG_ORIE_BIT      (1<<3)
#define MCF_SCIC3_REG_NEIE_BIT      (1<<2)
#define MCF_SCIC3_REG_FEIE_BIT      (1<<1)
#define MCF_SCIC3_REG_PEIE_BIT      (1<<0)


/* Bit definition for SCIS1 register */
#define MCF_SCIS1_REG_TDRE_BIT      (1<<7)
#define MCF_SCIS1_REG_TC_BIT        (1<<6)
#define MCF_SCIS1_REG_RDRF_BIT      (1<<5)
#define MCF_SCIS1_REG_IDLE_BIT      (1<<4)
#define MCF_SCIS1_REG_OR_BIT        (1<<3)
#define MCF_SCIS1_REG_NF_BIT        (1<<2)
#define MCF_SCIS1_REG_FE_BIT        (1<<1)
#define MCF_SCIS1_REG_PE_BIT        (1<<0)


/* Bit definition for SCIS2 register */
#define MCF_SCIS2_REG_LBKDIF_BIT    (1<<7)
#define MCF_SCIS2_REG_RXEDGIF_BIT   (1<<6)
#define MCF_SCIS2_REG_RXINV_BIT     (1<<4)
#define MCF_SCIS2_REG_RWUID_BIT     (1<<3)
#define MCF_SCIS2_REG_BRK13_BIT     (1<<2)
#define MCF_SCIS2_REG_LBKDE_BIT     (1<<1)
#define MCF_SCIS2_REG_RAF_BIT       (1<<0)


/* MCG */
#define MCF_MCGC1_REG     (*(hcc_reg8*)(&_IPSBAR[0x48]))
#define MCF_MCGC2_REG     (*(hcc_reg8*)(&_IPSBAR[0x49]))
#define MCF_MCGTRM_REG     (*(hcc_reg8*)(&_IPSBAR[0x4A]))
#define MCF_MCGSC_REG     (*(hcc_reg8*)(&_IPSBAR[0x4B]))
#define MCF_MCGC3_REG     (*(hcc_reg8*)(&_IPSBAR[0x4C]))
#define MCF_MCGT_REG     (*(hcc_reg8*)(&_IPSBAR[0x4D]))

/* Bit defintions for MCGC1 register */
#define MCF_MCGC1_REG_CLKS_BIT    (3<<6)
#define MCF_MCGC1_REG_RDIV_BIT    (7<<3)
#define MCF_MCGC1_REG_IREFS_BIT   (1<<2)
#define MCF_MCGC1_REG_IRCLKEN_BIT (1<<1)
#define MCF_MCGC1_REG_IREFSTEN_BIT    (1)


/* Bit defintions for MCGC2 register */
#define MCF_MCGC2_REG_BDIV_BIT    (2<<6)
#define MCF_MCGC2_REG_RANGE_BIT   (1<<5)
#define MCF_MCGC2_REG_HGO_BIT     (1<<4)
#define MCF_MCGC2_REG_LP_BIT      (1<<3)
#define MCF_MCGC2_REG_EREFS_BIT   (1<<2)
#define MCF_MCGC2_REG_ERCLKEN_BIT (1<<1)
#define MCF_MCGC2_REG_EREFSTEN_BIT    (1)


/* Bit defintions for MCGC3 register */
#define MCF_MCGC3_REG_LOLIE_BIT   (1<<7)
#define MCF_MCGC3_REG_PLLS_BIT    (1<<6)
#define MCF_MCGC3_REG_CME_BIT     (1<<5)
#define MCF_MCGC3_REG_DIV32_BIT   (1<<4)
#define MCF_MCGC3_REG_VDIV_BIT    (1)


/* Bit defintions for MCGSC register */
#define MCF_MCGSC_REG_LOLS_BIT    (1<<7)
#define MCF_MCGSC_REG_LOCK_BIT    (1<<6)
#define MCF_MCGSC_REG_PLLST_BIT   (1<<5)
#define MCF_MCGSC_REG_IREFST_BIT  (1<<4)
#define MCF_MCGSC_REG_CLKST_BIT   (3<<2)
#define MCF_MCGSC_REG_OSCINIT_BIT (1<<1)
#define MCF_MCGSC_REG_FTRIM_BIT   (1)


/* Real Time Clock */
#define MCF_RTCSC_REG		  (*(hcc_reg8*)(&_IPSBAR[0x6C]))
#define MCF_RTCCNT_REG		(*(hcc_reg8*)(&_IPSBAR[0x6D]))
#define MCF_RTCMOD_REG		(*(hcc_reg8*)(&_IPSBAR[0x6E]))

/* Bit definitions for RTC */
#define MCF_RTCSC_REG_RTIE_BIT  (1<<4)
#define MCF_RTCSC_REG_RTIF_BIT  (1<<7)

/* Bit values for RTC */
#define MCF_RTC_SOURCE_LPO   0
#define MCF_RTC_SOURCE_EXT   1
#define MCF_RTC_SOURCE_INT   2


/* Timer/PWM */
#define MCF_TPM1SC_REG        (*(hcc_reg8*)(&_IPSBAR[0x20]))
#define MCF_TPM1CNTH_REG      (*(hcc_reg8*)(&_IPSBAR[0x21]))
#define MCF_TPM1CNTL_REG      (*(hcc_reg8*)(&_IPSBAR[0x22]))
#define MCF_TPM1MODH_REG      (*(hcc_reg8*)(&_IPSBAR[0x23]))
#define MCF_TPM1MODL_REG      (*(hcc_reg8*)(&_IPSBAR[0x24]))
#define MCF_TPM1C0SC_REG      (*(hcc_reg8*)(&_IPSBAR[0x25]))
#define MCF_TPM1C0VH_REG      (*(hcc_reg8*)(&_IPSBAR[0x26]))
#define MCF_TPM1C0VL_REG      (*(hcc_reg8*)(&_IPSBAR[0x27]))
#define MCF_TPM1C1SC_REG      (*(hcc_reg8*)(&_IPSBAR[0x28]))
#define MCF_TPM1C1VH_REG      (*(hcc_reg8*)(&_IPSBAR[0x29]))
#define MCF_TPM1C1VL_REG      (*(hcc_reg8*)(&_IPSBAR[0x2A]))
#define MCF_TPM1C2SC_REG      (*(hcc_reg8*)(&_IPSBAR[0x2B]))
#define MCF_TPM1C2VH_REG      (*(hcc_reg8*)(&_IPSBAR[0x2C]))
#define MCF_TPM1C2VL_REG      (*(hcc_reg8*)(&_IPSBAR[0x2D]))
#define MCF_TPM1C3SC_REG      (*(hcc_reg8*)(&_IPSBAR[0x2E]))
#define MCF_TPM1C3VH_REG      (*(hcc_reg8*)(&_IPSBAR[0x2F]))
#define MCF_TPM1C3VL_REG      (*(hcc_reg8*)(&_IPSBAR[0x30]))

/* Timer/PWM word type registers */
#define MCF_TPM1CNT_REG      (*(hcc_reg16*)(&_IPSBAR[0x21]))  /* this may be problem because it is not aligned to word boundary.*/
#define MCF_TPM1MOD_REG      (*(hcc_reg16*)(&_IPSBAR[0x23]))  /* same boundary issue as above */
#define MCF_TPM1C0V_REG      (*(hcc_reg16*)(&_IPSBAR[0x26]))
#define MCF_TPM1C1V_REG      (*(hcc_reg16*)(&_IPSBAR[0x29]))
#define MCF_TPM1C2V_REG      (*(hcc_reg16*)(&_IPSBAR[0x2C]))
#define MCF_TPM1C3V_REG      (*(hcc_reg16*)(&_IPSBAR[0x2F]))

#define MCF_TPMxSC_REG        MCF_TPM1SC_REG
#define MCF_TPMxCNT_REG       MCF_TPM1CNT_REG
#define MCF_TPMxMOD_REG       MCF_TPM1MOD_REG
#define MCF_TPMxMODH_REG      MCF_TPM1MODH_REG
#define MCF_TPMxMODL_REG      MCF_TPM1MODL_REG
#define MCF_TPMxCnSC_REG      MCF_TPM1C0SC_REG
#define MCF_TPMxCnV_REG       MCF_TPM1C0V_REG


/* Bit/Bit mask definitions for TPMxSC register */
#define MCF_TPMSC_REG_TOF_BIT   (1<<7)   
#define MCF_TPMSC_REG_TOIE_BIT  (1<<6)
#define MCF_TPMSC_REG_CPWMS_BIT (1<<5)
#define MCF_TPMSC_REG_CLKS_BIT  (3<<3)
#define MCF_TPMSC_REG_CLKS_BIT_POS  (3)
#define MCF_TPMSC_REG_PS_BIT    (7)

/* TPM Prescaler */
#define MCF_TPM_CLK_PRESCALOR_1   0
#define MCF_TPM_CLK_PRESCALOR_2   1
#define MCF_TPM_CLK_PRESCALOR_4   2
#define MCF_TPM_CLK_PRESCALOR_8   3
#define MCF_TPM_CLK_PRESCALOR_16  4
#define MCF_TPM_CLK_PRESCALOR_32  5
#define MCF_TPM_CLK_PRESCALOR_64  6
#define MCF_TPM_CLK_PRESCALOR_128 7


/* Bit/Bit mask definitions for TPMxCnSC register */
#define MCF_TPMCnSC_REG_CHnF_BIT   (1<<7)   
#define MCF_TPMCnSC_REG_CHnIE_BIT  (1<<6)   
#define MCF_TPMCnSC_REG_MSnBA_BIT_POS 4 
#define MCF_TPMCnSC_REG_MSnBA_BIT  (3<<MCF_TPMCnSC_REG_MSnBA_BIT_POS)
#define MCF_TPMCnSC_REG_ELSn_BIT_POS  2  
#define MCF_TPMCnSC_REG_ELSn_BIT   (2<<MCF_TPMCnSC_REG_ELSn_BIT_POS)   

/* Mode, edge and level selection */
#define MCF_TPM_MODE_INPUT_CAPTURE  0    /* CPWMS = 0 in TPMSC register */ 
#define MCF_TPM_MODE_OUTPUT_COMPARE (1 << MCF_TPMCnSC_REG_MSnBA_BIT_POS)    /* CPWMS = 0 in TPMSC register */
#define MCF_TPM_MODE_PWM_EDGE       (2 << MCF_TPMCnSC_REG_MSnBA_BIT_POS)    /* CPWMS = 0 in TPMSC register */
#define MCF_TPM_MODE_PWM_CENTER     MCF_TPMSC_REG_CPWMS_BIT    /* CPWMS = 1 in TPMSC register */

#define MCF_TPM_EDGE_RISING         (1 << MCF_TPMCnSC_REG_ELSn_BIT_POS)
#define MCF_TPM_EDGE_FALLING        (2 << MCF_TPMCnSC_REG_ELSn_BIT_POS)
#define MCF_TPM_EDGE_BOTH           (3 << MCF_TPMCnSC_REG_ELSn_BIT_POS)

#define MCF_TPM_OUTPUT_SW           0
#define MCF_TPM_OUTPUT_TOGGLE       (1 << MCF_TPMCnSC_REG_ELSn_BIT_POS)
#define MCF_TPM_OUTPUT_CLEAR        (2 << MCF_TPMCnSC_REG_ELSn_BIT_POS)
#define MCF_TPM_OUTPUT_SET          (3 << MCF_TPMCnSC_REG_ELSn_BIT_POS)

#define MCF_TPM_PWM_OUTPUT_HIGH       MCF_TPM_OUTPUT_CLEAR
#define MCF_TPM_PWM_OUTPUT_LOW        MCF_TPM_OUTPUT_SET

/* Input capture macros */
#define MCF_TPM_MODE_INPUT_CAPTURE_RISING_EDGE  ( MCF_TPM_MODE_INPUT_CAPTURE |  MCF_TPM_EDGE_RISING)
#define MCF_TPM_MODE_INPUT_CAPTURE_FALLING_EDGE  ( MCF_TPM_MODE_INPUT_CAPTURE |  MCF_TPM_EDGE_FALLING)
#define MCF_TPM_MODE_INPUT_CAPTURE_BOTH_EDGE  ( MCF_TPM_MODE_INPUT_CAPTURE |  MCF_TPM_EDGE_BOTH)

/* Output compare macros */
#define MCF_TPM_MODE_OUTPUT_COMPARE_SW        (MCF_TPM_MODE_OUTPUT_COMPARE |  MCF_TPM_OUTPUT_SW)
#define MCF_TPM_MODE_OUTPUT_COMPARE_TOGGLE    (MCF_TPM_MODE_OUTPUT_COMPARE |  MCF_TPM_OUTPUT_TOGGLE)
#define MCF_TPM_MODE_OUTPUT_COMPARE_CLEAR     (MCF_TPM_MODE_OUTPUT_COMPARE |  MCF_TPM_OUTPUT_CLEAR)
#define MCF_TPM_MODE_OUTPUT_COMPARE_SET       (MCF_TPM_MODE_OUTPUT_COMPARE |  MCF_TPM_OUTPUT_SET)

/* Clock source selection */
#define MCF_TPM_CLK_SRC_NO          0
#define MCF_TPM_CLK_SRC_BUS_CLK     (1<<MCF_TPMSC_REG_CLKS_BIT_POS)
#define MCF_TPM_CLK_SRC_FIX_CLK     (2<<MCF_TPMSC_REG_CLKS_BIT_POS)
#define MCF_TPM_CLK_SRC_EXT_CLK     (3<<MCF_TPMSC_REG_CLKS_BIT_POS)

/* Port D register definitions */
#define  MCF_PTDD_REG         (*(hcc_reg8*)(&_IPSBAR[0x6]))
#define  MCF_PTDDD_REG        (*(hcc_reg8*)(&_IPSBAR[0x7]))
#define   MCF_PTDPE_REG        (*(hcc_reg8*)(&_IPSBAR[0x184C]))
#define   MCF_PTDSE_REG        (*(hcc_reg8*)(&_IPSBAR[0x184D]))
#define   MCF_PTDDS_REG        (*(hcc_reg8*)(&_IPSBAR[0x184E]))
#define   MCF_PTDIFE_REG       (*(hcc_reg8*)(&_IPSBAR[0x184F]))


/* System Integration Module (Refer to Chapter 5 of Soc Guide) */
#define MCF_SIMOPT1_REG       (*(hcc_reg8*)(&_IPSBAR[0x1802]))
#define MCF_SIMOPT2_REG       (*(hcc_reg8*)(&_IPSBAR[0x1803]))

#define MCF_SIMOPT1_REG_COPT_BIT  (3<<6)


/* Flash */
#define MCF_FCDIV_REG       (*(hcc_reg8*)(&_IPSBAR[0x1820]))
#define MCF_FOPT_REG        (*(hcc_reg8*)(&_IPSBAR[0x1821]))
#define MCF_FRSV0_REG       (*(hcc_reg8*)(&_IPSBAR[0x1822]))
#define MCF_FCNFG_REG       (*(hcc_reg8*)(&_IPSBAR[0x1823]))
#define MCF_FPROT_REG       (*(hcc_reg8*)(&_IPSBAR[0x1824]))
#define MCF_FSTAT_REG       (*(hcc_reg8*)(&_IPSBAR[0x1825]))
#define MCF_FCMD_REG        (*(hcc_reg8*)(&_IPSBAR[0x1826]))
#define MCF_FRSV1_REG       (*(hcc_reg8*)(&_IPSBAR[0x1827]))
#define MCF_FADDRHI_REG     (*(hcc_reg8*)(&_IPSBAR[0x1828]))
#define MCF_FADDRLO_REG     (*(hcc_reg8*)(&_IPSBAR[0x1829]))
#define MCF_FRSV2_REG       (*(hcc_reg8*)(&_IPSBAR[0x182A]))
#define MCF_FRSV3_REG       (*(hcc_reg8*)(&_IPSBAR[0x182B]))
#define MCF_FDATAHI1_REG    (*(hcc_reg8*)(&_IPSBAR[0x182C]))
#define MCF_FDATALO1_REG       (*(hcc_reg8*)(&_IPSBAR[0x182D]))
#define MCF_FDATAHI0_REG       (*(hcc_reg8*)(&_IPSBAR[0x182E]))
#define MCF_FDATALO0_REG       (*(hcc_reg8*)(&_IPSBAR[0x182F]))




/* Interrupt No. */
#define VectorNumber_VRTC     VectorNumber_Vrtc //29
#define VectorNumber_TPM1Ovf    VectorNumber_Vtpm1ovf   
#define VectorNumber_TPM1CH0F    VectorNumber_Vtpm1ch0

#define VectorNumber_TICK1ms  VectorNumber_TPM1CH0F //VectorNumber_TPM1

#endif
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