max3490.map.qmsg

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· QMSG 代码 · 共 47 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 30 00:04:10 2008 " "Info: Processing started: Mon Jun 30 00:04:10 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MAX3490 -c MAX3490 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MAX3490 -c MAX3490" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MAX3490.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MAX3490.v" { { "Info" "ISGN_ENTITY_NAME" "1 MAX3490 " "Info: Found entity 1: MAX3490" {  } { { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "MAX3490 " "Info: Elaborating entity \"MAX3490\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "rs232rx.v 1 1 " "Warning: Using design file rs232rx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 rs232rx " "Info: Found entity 1: rs232rx" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232rx rs232rx:m1 " "Info: Elaborating entity \"rs232rx\" for hierarchy \"rs232rx:m1\"" {  } { { "MAX3490.v" "m1" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 159 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rs232rx.v(174) " "Warning (10230): Verilog HDL assignment warning at rs232rx.v(174): truncated value with size 32 to match size of target (1)" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rs232rx.v(185) " "Warning (10230): Verilog HDL assignment warning at rs232rx.v(185): truncated value with size 32 to match size of target (1)" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 185 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rs232rx.v(186) " "Warning (10230): Verilog HDL assignment warning at rs232rx.v(186): truncated value with size 32 to match size of target (1)" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 186 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rs232rx.v(191) " "Warning (10230): Verilog HDL assignment warning at rs232rx.v(191): truncated value with size 32 to match size of target (1)" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 191 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rs232rx.v(192) " "Warning (10230): Verilog HDL assignment warning at rs232rx.v(192): truncated value with size 32 to match size of target (1)" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 192 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rs232rx.v(194) " "Warning (10230): Verilog HDL assignment warning at rs232rx.v(194): truncated value with size 32 to match size of target (1)" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 194 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 rs232rx.v(205) " "Warning (10230): Verilog HDL assignment warning at rs232rx.v(205): truncated value with size 32 to match size of target (4)" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 205 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 rs232rx.v(214) " "Warning (10230): Verilog HDL assignment warning at rs232rx.v(214): truncated value with size 32 to match size of target (10)" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 214 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "rs232tx.v 1 1 " "Warning: Using design file rs232tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 rs232tx " "Info: Found entity 1: rs232tx" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 34 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}