pcisim.c

此代码用于生成测试PCI设备的Verilog代码（Verilog代码为一种硬件描述语言）。此代码可以直接运行于LINUX下。

/*
 * Copyright (c) 2002 Picture Elements, Inc.
 *    Stephen Williams ([e-mail])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
 *    General Public License as published by the Free Software
 *    Foundation; either version 2 of the License, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
#ident "$Id: pcisim.c,v 1.4 2002/10/16 16:54:24 steve Exp $"

# include  <stdio.h>
# include  <stdlib.h>
# include  <sys/types.h>
# include  <sys/stat.h>
# include  <fcntl.h>
# include  <errno.h>
# include  <assert.h>

# include  "pcisim.h"
# include  "priv.h"

static const char*pci_fifo0 = "pci_fifo0";
static const char*pci_fifo1 = "pci_fifo1";

FILE*cfd0 = 0;
FILE*cfd1 = 0;

void pcisim_init(void)
{
      int rc;

      for (;;) {
	    rc = open(pci_fifo0, O_WRONLY, 0);
	    if (rc >= 0)
		  break;

	    if (errno != ENOENT) {
		  fprintf(stderr, "%s: error opening pipe.\n", pci_fifo0);
		  exit(1);
	    }

	    fprintf(stderr, "** Waiting for simulation process...\n");
	    sleep(1);
      }

      assert(rc >= 0);

      cfd0 = fdopen(rc, "w");

      for (;;) {
	    rc = open(pci_fifo1, O_RDONLY, 0);
	    if (rc >= 0)
		  break;

	    if (errno != ENOENT) {
		  fprintf(stderr, "%s: error opening pipe.\n", pci_fifo1);
		  exit(1);
	    }

	    fprintf(stderr, "** Waiting for simulation process...\n");
	    sleep(1);
      }

      cfd1 = fdopen(rc, "r");

      fprintf(stderr, "** Connected to simulation process.\n");
}

unsigned pcisim_wait(unsigned clks, unsigned irq_enable)
{
      int rc;
      unsigned tmp1, value;
      char buf[64];

      sprintf(buf, "0x10 %u %u\n", clks, irq_enable&0xffff);
      fputs(buf, cfd0);
      fflush(cfd0);

      fgets(buf, sizeof buf, cfd1);

	/* The response from the device is a bitmask of active
	   interrupts. */
      rc = sscanf(buf, " %x %x", &tmp1, &value);
      assert(rc == 2);
      return value;
}

void pcisim_reset(unsigned width, unsigned settle)
{
      char buf[64];

	/* Set the RESET# low */
      sprintf(buf, "0x20 0\n");
      fputs(buf, cfd0);
      fflush(cfd0);

      fgets(buf, sizeof buf, cfd1);

      pcisim_wait(width, 0);

	/* Set the RESET# high */
      sprintf(buf, "0x20 1\n");
      fputs(buf, cfd0);
      fflush(cfd0);

      fgets(buf, sizeof buf, cfd1);

      if (settle > 0)
	    pcisim_wait(settle, 0);
}

void pcisim_end_simulation(void)
{
      char buf[64];

      sprintf(buf, "0x00\n");
      fputs(buf, cfd0);
      fflush(cfd0);
}


/*
 * $Log: pcisim.c,v $
 * Revision 1.4  2002/10/16 16:54:24  steve
 *  Copyright and License notice.
 *
 * Revision 1.3  2002/07/01 19:40:09  steve
 *  Wait for simulation process.
 *
 * Revision 1.2  2002/06/01 02:22:06  steve
 *  Extend pcisim_wait to wait for interrupts.
 *
 * Revision 1.1  2002/05/12 22:17:17  steve
 *  Add pcisim to CVS.
 *
 */