pcisim_readl.c

此代码用于生成测试PCI设备的Verilog代码（Verilog代码为一种硬件描述语言）。此代码可以直接运行于LINUX下。

/*
 * Copyright (c) 2002 Picture Elements, Inc.
 *    Stephen Williams ([e-mail])
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
 *    General Public License as published by the Free Software
 *    Foundation; either version 2 of the License, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
#ident "$Id: pcisim_readl.c,v 1.4 2003/05/27 23:59:57 steve Exp $"

# include  <stdio.h>
# include  <stdlib.h>
# include  "pcisim.h"
# include  "priv.h"
# include  <assert.h>

unsigned long pcisim_readl(unsigned long addr)
{
      unsigned tmp1, tmp2, value;
      int rc;
      char buf[64];

      sprintf(buf, "0x06 0x%lx 1\n", addr);
      fputs(buf, cfd0);
      fflush(cfd0);

      fgets(buf, sizeof buf, cfd1);

      rc = sscanf(buf, " %x %x %x", &tmp1, &tmp2, &value);
      assert(rc == 3);
      return value;
}

void pcisim_writel(unsigned long addr, unsigned long word)
{
      char buf[64];

      sprintf(buf, "0x07 0x%lx 0x%lx 0x00\n", addr, word);
      fputs(buf, cfd0);
      fflush(cfd0);

      fgets(buf, sizeof buf, cfd1);
}

void pcisim_writel_x(unsigned long addr, unsigned long word, int mask)
{
      char buf[64];

      sprintf(buf, "0x07 0x%lx 0x%lx 0x%x\n", addr, word, mask&0x0f);
      fputs(buf, cfd0);
      fflush(cfd0);

      fgets(buf, sizeof buf, cfd1);
}



/*
 * $Log: pcisim_readl.c,v $
 * Revision 1.4  2003/05/27 23:59:57  steve
 *  Support explicit byte lane controls on write.
 *
 * Revision 1.3  2002/10/16 16:54:24  steve
 *  Copyright and License notice.
 *
 * Revision 1.2  2002/05/12 23:53:14  steve
 *  Add memory write cycles to master and memory.
 *
 * Revision 1.1  2002/05/12 22:17:17  steve
 *  Add pcisim to CVS.
 *
 */