data_16qam_map.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

module DATA_16QAM_mapper(DM_DIN,DM_ND,DM_RST,DM_CLK,DM_RE,DM_IM,DM_INDEX,
                      DM_RDY);
	input DM_DIN;	   //输入信号
	input DM_CLK;	   //脉冲
	input DM_ND;	   //来自上一模块的信号提示
	input DM_RST;		//复位信号
	output[7:0] DM_RE;	//输出16QAM调制的实部，八位，一位符号位，一位整数位，六位小数位
	output[7:0] DM_IM;	//输出16QAM调制的虚部
	output[5:0] DM_INDEX;//输出标号
	output DM_RDY;		//输出信号提示
	
	reg[7:0] DM_RE;
	reg[7:0] DM_IM;
	reg DM_RDY;
	reg[7:0] RE_TEMP;	//输出实部暂存
	reg[7:0] IM_TEMP;	//输出虚部暂存
	reg[3:0] STOR;		//由于四个输入信号对应一个星座点，因此需要四位的存储器存放
	reg MAPEN;
	reg[5:0] DM_COUNT;
	reg[5:0] DM_INDEX;	
	reg OUTEN;		//使Q_RDY比输入四个信号中最后一个晚一个脉冲的过渡，保证转换完成
	reg[1:0] counter;	//四个输入信号的计数
	reg[1:0] OUT_COUNT;


always @(negedge DM_RST or posedge DM_CLK) 	//Q_RST高电平异步清零
    if(!DM_RST)
       begin
	  MAPEN<=1'b0;
       DM_RE[7:0]<=8'b00000000;
	  DM_IM[7:0]<=8'b00000000;
	  DM_COUNT[5:0]<=6'b000000;
	  DM_INDEX[5:0]<=6'b000000;
	  DM_RDY<=0;
	  RE_TEMP[7:0]<=8'b00000000;
	  IM_TEMP[7:0]<=8'b00000000;
	  STOR[3:0]<=4'b0000;
	  OUTEN<=0;
	  counter[1:0]<=2'b00;
	  OUT_COUNT<=2'b00;
	  end

     else
	 begin
	   if(DM_ND)		  //16QAM encoding
	    begin
	       counter<=counter+1;
		  case(counter)
		    	 2'b00:STOR[0]<=DM_DIN;
			 2'b01:STOR[1]<=DM_DIN;	       //存入输入数值
			 2'b10:STOR[2]<=DM_DIN;
			 2'b11:STOR[3]<=DM_DIN;
		   endcase
         end
       else
	    begin
	    	  counter[1:0]<=2'b00; 
		  STOR[3:0]<=4'b0000;
         end

       if (counter==2'b11)       // MAPEN 标记四个信号是否已经存入
	    MAPEN<=1'b1;
       else
	    MAPEN<=1'b0;  

		  if(MAPEN)
		    begin
		   	case(STOR[1:0])
		      2'b00:RE_TEMP[7:0]<=8'b11000011;
			 2'b10:RE_TEMP[7:0]<=8'b11101100;
			 2'b01:RE_TEMP[7:0]<=8'b00111101;
			 2'b11:RE_TEMP[7:0]<=8'b00010100; 
		   	endcase
			case(STOR[3:2])
			2'b00:IM_TEMP[7:0]<=8'b11000011;
			2'b10:IM_TEMP[7:0]<=8'b11101100;
			2'b01:IM_TEMP[7:0]<=8'b00111101;
		     2'b11:IM_TEMP[7:0]<=8'b00010100;
			endcase
			OUTEN<=1;
			end
             else
		     begin
		     OUTEN<=0;
			RE_TEMP[7:0]<=8'b00000000;
			IM_TEMP[7:0]<=8'b00000000;
			end

		if(OUTEN)                            // 输出
		   begin
		   DM_RE<=RE_TEMP;
	   	   DM_IM<=IM_TEMP;
	        DM_COUNT<=DM_COUNT+1;
		   DM_INDEX<=DM_COUNT;
		   DM_RDY<=1'b1;
             end
	    
	     if (DM_INDEX==47)
		   OUT_COUNT<=OUT_COUNT+1;
          else
		   OUT_COUNT<=0;

          if (OUT_COUNT==2'b11)
		   begin
		   DM_RE[7:0]<=8'b00000000;
		   DM_IM[7:0]<=8'b00000000;
		   DM_INDEX[5:0]<=6'b000000;
		   DM_COUNT[5:0]<=6'b000000;
		   DM_RDY<=0;
		   end
	end
  
endmodule