transmit_mcu.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

module TX_MCU(PHY_TXSTART,TXSTART_REQ,DATA_CONF,DATA_IN,MAC_CLK,SYS_CLK,
                 MCU_RST,GLB_RST,PHY_RST,LENGTH,RATE,TXPWR,SHORT_ACK,LONG_ACK,
                 SIG_ACK,DATA_REQ,DATA_START,DATA_OUT,DATA_DV,FFT_SET,FFT_EN_Q,
			        RATE_CON,SCRAM_SEED);
    input PHY_TXSTART;
    input TXSTART_REQ;
    input DATA_CONF;
    input [7:0] DATA_IN;
    input MAC_CLK;
    input SYS_CLK;
    input MCU_RST;
    input GLB_RST;
    output PHY_RST;
    output [11:0] LENGTH;
    output [5:0] RATE;
    output [2:0] TXPWR;
    output SHORT_ACK;
    output LONG_ACK;
    output SIG_ACK;
    output DATA_REQ;
    output DATA_START;
    output [7:0] DATA_OUT;
    output DATA_DV;
    output FFT_SET;
    output FFT_EN_Q;
    output [3:0] RATE_CON;
    output [6:0] SCRAM_SEED;



    wire [4:0] TXPAR_BUFADDR;          //transmit parameters buffer address signal
    wire THRESH1;                      //transmit parameters buffer over signal
    wire [8:0] MCOUNTER;               //U_MAIN_COUNTER outputs
    wire [6:0] COUNT80;                //U_COUNT80 outputs
    wire FFT_EN;                       //signal for FFT transform starting
    wire [4:0] COUNT_DATA;             //U_COUNT_DATA outputs
    wire DATA_TXSTART;			    //the signal for starting the DATA field transmission
    wire [4:0] COUNT30;                //U_COUNT30 outputs
    wire REQ;			              //the signal asking for the Data Octs from MAC
    wire GLB_RST_H;                    //Reset signal for IP core U_TXPAR_BUFADDR 
    wire RST;                          //Reset signal for IP cores except U_TXPAR_BUFADDR

    reg [20:0] TXPAR_BUF;              //transmit parameters buffer
    reg PHY_RST;                       //transmit initialize signal
    reg [11:0] LENGTH;			    //transmit parameters: data length
    reg [5:0] RATE;				    //transmit parameters: data rate
    reg [2:0] TXPWR;			    //transmit parameters: transmit power
    reg MCOUNTER_CE;                   //U_MAIN_COUNTER enable signal
    reg BUF_OVER;				    //The register for the transmit parameters buffer over signal
    reg SHORT_ACK;				    //short sequences transmission start signal
    reg LONG_ACK;				    //Long sequences transmission enable signal
    reg SIG_ACK; 				    //Signal field process start signal
    reg FFT_SET;                       //FFTPro module initialize signal
    reg COUNT80_CE;                    //U_COUNT80 enable signal
    reg FFT_EN_Q;                      //register of signal FFT_EN
    reg [13:0] N_SYM_FFT;	         //Counter for the number of symbols to help generate FFT_EN signal, add one bit as the sign bit
    reg COUNT_DATA_CE;                 //U_COUNT_DATA enable signal
    reg COUNT30_CE;                    //U_COUNT30 enable signal
    reg [13:0] N_SYM_DATA;	         //Counter for the number of symbols to help generate DATA_REQ signal, add one bit as the sign bit
    reg DATA_REQ;                      //Register for signal REQ 
    reg [7:0] DATA_BUF;                //The input buffer for DATA_IN
    reg DATA_RDY;                	    //The signal indicationg that DATA have been inputted
    reg DATA_START;             	    //The signal enable DATA_generator
    reg [7:0] DATA_OUT;                //DATA output register
    reg DATA_DV;                	    //The signal indicationg  DATA valid 
    reg RST_CON;                       //The signal helping generate PHY_RST    
    reg [3:0] RATE_CON;			    //RATE_CON is used for DATA_generator to control its coding and mapping
    reg [6:0] SCRAM_SEED;		    //The signal for scrambler of DATA_generator to initialize its LSFR
    reg FFT_EN_Q1;
    reg SHORT_ACK1;

    assign GLB_RST_H=~GLB_RST;                
    assign RST=~MCU_RST;

//TXSTART_REQ is enabled to convert the transmitter into transmit state.
//The transmit parameters are buffered.

counter21 U_TXPAR_BUFADDR (			      //counter21 for buffer addresses generation
    .Q(TXPAR_BUFADDR),
    .CLK(MAC_CLK),
    .Q_THRESH1(THRESH1),
    .CE(TXSTART_REQ),
    .AINIT(GLB_RST_H)); 

always @ (negedge GLB_RST or posedge MAC_CLK)	   
if (!GLB_RST)						//These signals can only be reset by the global reset	 
  begin								 //signal but not PHY_RST.
  TXPAR_BUF<=0;
  PHY_RST<=1;
  RST_CON<=0;
  BUF_OVER<=0;
  LENGTH<=0;
  RATE<=0;
  TXPWR<=0;
  end

else
  begin
  if (TXSTART_REQ)                //transmit parameters are buffered into TXPAR_BUF by  
    begin								 //control of TXSTART_REQ  
    TXPAR_BUF[TXPAR_BUFADDR]<=PHY_TXSTART;
    end
  
  if	(TXSTART_REQ && !RST_CON)	//RST_CON will be set 1 to prevent PHY_RST from getting low again
    begin
    PHY_RST<=0;						 //transmit initialize
    RST_CON<=1;
    end
  else if (!TXSTART_REQ)
    RST_CON<=0;

  if (!PHY_RST)						 //PHY_RST gets low(valid) for 1 clock
    PHY_RST<=1;

  if (THRESH1)
    BUF_OVER<=1;
  else
    BUF_OVER<=0;

  if (BUF_OVER)						 //BUF_OVER will get high for one clock after transmit 
    begin								 //parameters are buffered.
    LENGTH<=TXPAR_BUF[20:9];		 //Transmit parameters will be put out by the control of
    RATE<=TXPAR_BUF[8:3];			 //BUF_OVER
    TXPWR<=TXPAR_BUF[2:0];
    end
  else if (!TXSTART_REQ) 								 
    TXPAR_BUF<=0;						 //When output is finished, TXPAR_BUF will be cleared. 
  
  end


//transmit control signals generation and output

main_counter U_MAIN_COUNTER (				 //The main counter for transmit sequences 
    .Q(MCOUNTER),
    .CLK(SYS_CLK),
    .CE(MCOUNTER_CE),
    .ACLR(RST));
													//The counter to generate FFT_EN signals
counter_80 U_COUNT80 (
    .Q(COUNT80),
    .CLK(SYS_CLK),
    .THRESH1(FFT_EN),
    .CE(COUNT80_CE),
    .ACLR(RST));

always @ (negedge MCU_RST or posedge SYS_CLK)	   
if (!MCU_RST)								 
  begin
  MCOUNTER_CE<=0;
  N_SYM_FFT<=0;
  SHORT_ACK<=0;
  LONG_ACK<=0;
  SIG_ACK<=0;
  FFT_SET<=0;
  COUNT80_CE<=0;
  FFT_EN_Q<=0;
  FFT_EN_Q1<=0;
  SCRAM_SEED<=0;
  RATE_CON<=0;
  end

else
  begin
  if (BUF_OVER)        			    //if BUF_OVER is enabled, the U_MAIN_COUNTER will be started 
    begin								 //as well as the transmission of short sequences
    MCOUNTER_CE<=1;
    SHORT_ACK1<=1;
    N_SYM_FFT<=TXPAR_BUF[20:9]+21;		     
	 //N_SYM_FFT will be set the number of length, add 21 for the service field,
    //tail bits and signal field (2.75+18).
    SCRAM_SEED<=7'b1011101;
    case (TXPAR_BUF[8:3])                     // RATE_CON is from the vector of RATE.
        6'd6 : RATE_CON<=4'b1101 ;
	   6'd9 : RATE_CON<=4'b1111 ;
	   6'd12: RATE_CON<=4'b0101 ;
	   6'd18: RATE_CON<=4'b0111 ;
	   6'd24: RATE_CON<=4'b1001 ;
	   6'd36: RATE_CON<=4'b1011 ;
	   6'd48: RATE_CON<=4'b0010 ;
	   6'd54: RATE_CON<=4'b0011 ;
      default: RATE_CON<=4'b0000 ;
      endcase
    end  

	if(SHORT_ACK1)
		SHORT_ACK1<=~SHORT_ACK1;

  if (SHORT_ACK1)                          
    SHORT_ACK<=1;
  if (MCOUNTER==161)              //"MCOUNTER==160" can stop the short sequences transmission
    SHORT_ACK<=0;

  if (MCOUNTER==160)					 //When MCOUNTER equals to 159, long sequences will begin to transmit 
    LONG_ACK<=1;						 //and stop after 161 clocks. 

  if (MCOUNTER==42)               //MCOUNTER==42 can enable the SIG_ACK which will be high for 1 clock
    SIG_ACK<=1;
  else if (SIG_ACK)
    SIG_ACK<=~SIG_ACK;
  
  if (MCOUNTER==116)					 //MCOUNTER==116 will initialize the FFTpro module to make it ready for
    begin								 //process. U_COUNT80 will also be started for the output of FFT_EN. At 
    FFT_SET<=1;						 //the same time, the task of U_MAIN_COUNTER will be finished
    COUNT80_CE<=1;
    end
  else if (FFT_SET)
    FFT_SET<=~FFT_SET;

  if (MCOUNTER==321)					 //When MCOUNTER==320, the task of U_MAIN_COUNTER will be finished.
    begin								 //LONG_ACK will be also get low.
    MCOUNTER_CE<=0;
    LONG_ACK<=0;
    end

  if (FFT_EN)                                 //The FFT_EN is set into FFT_EN_Q and N_SYM_FFT is decreased by 18                            
    begin
    FFT_EN_Q1<=1;
    N_SYM_FFT<=N_SYM_FFT-18;
    end
  else
    FFT_EN_Q1<=0;

  if(FFT_EN_Q1)
  	FFT_EN_Q<=1;
  else if(FFT_EN_Q)
  	FFT_EN_Q<=~FFT_EN_Q;

  if (N_SYM_FFT==0 || N_SYM_FFT[13]==1'b1)    //If the N_SYM_FFT<=0, all the data have been transmitted, so U_COUNT80 will 
    COUNT80_CE<=0;						          //be stopped.

  end


//Generation of the signal DATA_REQ and completion of the DATA output
//Notice: It works by clock MAC_CLK, so it will be descripped  
//in another always block. 

counter_data U_COUNT_DATA (          //Counter for starting the DATA filed transmission
    .Q(COUNT_DATA),
    .CLK(MAC_CLK),
    .Q_THRESH1(DATA_TXSTART),
    .CE(COUNT_DATA_CE),
    .ACLR(RST));
									 
counter_30 U_COUNT30 (					 //The counter to generate DATA_REQ signals
    .Q(COUNT30),
    .CLK(MAC_CLK),
    .THRESH1(REQ),
    .CE(COUNT30_CE),
    .ACLR(RST));

always @ (negedge MCU_RST or posedge MAC_CLK) 	   
if (!MCU_RST)								 
  begin
  COUNT_DATA_CE<=0;
  N_SYM_DATA<=0;
  COUNT30_CE<=0;
  DATA_REQ<=0;
  DATA_BUF<=0;
  DATA_RDY<=0;
  DATA_START<=0;
  DATA_OUT<=0;
  DATA_DV<=0;
  end

else
  begin								 
  if (BUF_OVER)						 //U_COUNT_DATA is started by BUF_OVER. After counting 30 clocks,
    begin								 //DATA_REQ generation will be started.
    COUNT_DATA_CE<=1;						 
    N_SYM_DATA<=TXPAR_BUF[20:9]+3;		//N_SYM_DATA will be also initialized. 
    end

  if (DATA_TXSTART)                    //When DATA_TXSTART is high, COUNT30_CE will be started to  
    COUNT30_CE<=1;					      //generate the signal of  DATA_REQ.
    						       
  if (COUNT_DATA==30)				      //When COUNT_DATA equals to 30, U_COUNT_DATA will be stopped and 
    begin								      //the signal DATA_START will be also get high for 1 clock to 
    COUNT_DATA_CE<=0;					   //start DATA_generator.
    DATA_START<=1;
    end
  if (DATA_START==1)
    DATA_START<=~DATA_START;

  if (REQ)                             //REQ signal from U_COUNT30 will be output. At the same time,
    begin								      //N_SYM_DATA will be decreased by 18 to count the data num. 
    DATA_REQ<=1;
    N_SYM_DATA<=N_SYM_DATA-18;
    end
  else
    DATA_REQ<=0;

  if (N_SYM_DATA==0 || N_SYM_DATA[13]==1'b1)  //If the N_SYM_DATA<=0, all the data have been transmitted,  
    COUNT30_CE<=0;						          //so U_COUNT80 will be stopped
  
  if (DATA_CONF)						 //DATA input will be buffered with the control of input signal
    begin								 //DATA_CONF and the DATA_RDY will be get enabled to indicate 
    DATA_BUF<=DATA_IN;				 //DATA output can be started.
    DATA_RDY<=1;
    end
  else
    begin
    DATA_BUF<=0;
    DATA_RDY<=0;
    end

  if (DATA_RDY)						 //If the DATA_RDY is high, DATA will be outputted.
    begin
    DATA_OUT<=DATA_BUF;
    DATA_DV<=1;
    end
  else
    begin
    DATA_OUT<=0;
    DATA_DV<=0;
    end
      
  end

endmodule