data_interleaver.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

module DATA_interleaver(DINT_DIN,DINT_ND,INDEX_IN,DINT_RST,DINT_CLK,MODE_CON,
                           DINT_DOUT,DINT_RDY);
    input DINT_DIN;
    input DINT_ND;
    input [8:0] INDEX_IN;
    input [1:0] MODE_CON;
    input DINT_RST;
    input DINT_CLK;
    output DINT_DOUT;
    output DINT_RDY;

    reg DIN;             //register of input
    reg ND;					 //enable of output
    reg [8:0] INDEX;		 //register of index for output
    reg [1:0] MODE;		 
    reg [9:0] WA_1;      //DINT_RAM_1 write address
    reg DIN_1;           //DINT_RAM_1 input register
    reg REN_1;           //DINT_RAM_1 enable read 
	 reg WEN_1;           //DINT_RAM_1 enable write
    reg WAC_1;				 //control write address of 1st interleaver
    reg DINT_RDY_1;      //DINT_RAM_1 enable output
    reg DIN_2;				 //DINT_RAM_2 input register
    reg [4:0] WA_2;		 //DINT_RAM_2 write address
    reg WEN_2;				 //DINT_RAM_2 enable write
    reg REN_2;				 //DINT_RAM_2 enable read
    reg WAC_2;				 //control write address of 2ed interleaver
    reg DINT_DV;         //enable output
    reg DINT_DOUT;		 //output register
    reg DINT_RDY;			 //synchronize with output

    wire [9:0] RA_1;     //DINT_RAM_1 read address
    wire [9:0] Q_1;		 //RCOUNT_1 counter of output
    wire DOUT_1;         //DINT_RAM_1 output
    wire RST;            //reset of IP core, enable under high leavel
    wire [4:0] Q_2;		 //RCOUNT_2 counter of output
    wire [4:0] RA_2;		 //DINT_RAM_2 read address
    wire DOUT_2;         //DINT_RAM_2 output

  assign RST=~DINT_RST;       
  assign RA_1=Q_1;				

/********************************************************************************/
/****************************   register for input   ****************************/

always @ (negedge DINT_RST or posedge DINT_CLK)	   
if (!DINT_RST)								 
  begin
  DIN<=1'b0;
  ND<=1'b0;
  INDEX<=9'b000000000;
  MODE<=2'b00;
  end

else
  begin
  if (DINT_ND)
    begin
    DIN<=DINT_DIN;
    ND<=DINT_ND;
    INDEX<=INDEX_IN;
    MODE<=MODE_CON;
    end
  else 
    begin
    DIN<=1'b0;
    ND<=1'b0;
    INDEX<=9'b000000000;
    end
  end


/**********************************************************************************/
/****************************       DINT_RAM_1   ****************************/

// BRAM: depth is 384 bits, the 1st interleaver BRAM to store the data which already adjust the order

dint_ram DINT_RAM_1 (
    .addra(WA_1),
    .addrb(RA_1),
    .clka(DINT_CLK),
    .clkb(DINT_CLK),
    .dina(DIN_1),
    .doutb(DOUT_1),
    .enb(REN_1),
    .sinitb(RST),
    .wea(WEN_1));


/***************************************************************************/
/****************************       RCOUNT_1    ****************************/

// counter cycle is 384 to generate read address of DINT_RAM_1
										  
rcount_1 RCOUNT_1 (
    .Q(Q_1),
    .CLK(DINT_CLK),
    .CE(REN_1),                                           
    .ACLR(RST));


/**********************************************************************************/
/****************************       1st interleaver    ****************************/

always @ (negedge DINT_RST or posedge DINT_CLK)	   
if (!DINT_RST)								 
  begin
  WAC_1<=1'b0;
  WA_1<=10'b0000000000;
  WEN_1<=1'b0;
  DIN_1<=1'b0;
  REN_1<=1'b0;
  DINT_RDY_1<=1'b0;
  end

else
  begin
  case (MODE)									      
  2'b10: 
    begin
    if (ND)                                                  
      begin
      if (!WAC_1)						// input data write in the BRAM first half part and the end alternatively, under control of WAC_1. 		
	   WA_1<=(INDEX[3:0]<<3)+(INDEX[3:0]<<2)+INDEX[8:4];    	 
	 else	  	  	 				               
 	   WA_1<=(INDEX[3:0]<<3)+(INDEX[3:0]<<2)+INDEX[8:4]+192;                       														
	   WEN_1<=1'b1;									                                       
	   DIN_1<=DIN;															 
	 if (INDEX==191)