dint_ram2.asy

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

Version 4
SymbolType BLOCK
RECTANGLE Normal 32 0 448 544
PIN 0 48  LEFT 36
PINATTR PinName D[0:0]
PINATTR Polarity IN
LINE Wide 0 48 32 48
PIN 0 80  LEFT 36
PINATTR PinName A[4:0]
PINATTR Polarity IN
LINE Wide 0 80 32 80
PIN 0 112  LEFT 36
PINATTR PinName DPRA[4:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 240  LEFT 36
PINATTR PinName WE
PINATTR Polarity IN
LINE Normal 0 240 32 240
PIN 0 272  LEFT 36
PINATTR PinName CLK
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 336  LEFT 36
PINATTR PinName QDPO_CLK
PINATTR Polarity IN
LINE Normal 0 336 32 336
PIN 0 432  LEFT 36
PINATTR PinName QDPO_RST
PINATTR Polarity IN
LINE Normal 0 432 32 432
PIN 480 80  RIGHT 36
PINATTR PinName QSPO[0:0]
PINATTR Polarity OUT
LINE Wide 448 80 480 80
PIN 480 144  RIGHT 36
PINATTR PinName QDPO[0:0]
PINATTR Polarity OUT
LINE Wide 448 144 480 144
LINE Wide 448 144 480 144