dint_ram2.vhd

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

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-- You must compile the wrapper file dint_ram2.vhd when simulating
-- the core, dint_ram2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY dint_ram2 IS
	port (
	A: IN std_logic_VECTOR(4 downto 0);
	CLK: IN std_logic;
	D: IN std_logic_VECTOR(0 downto 0);
	WE: IN std_logic;
	DPRA: IN std_logic_VECTOR(4 downto 0);
	QDPO_CLK: IN std_logic;
	QDPO: OUT std_logic_VECTOR(0 downto 0);
	QSPO: OUT std_logic_VECTOR(0 downto 0);
	QDPO_RST: IN std_logic);
END dint_ram2;

ARCHITECTURE dint_ram2_a OF dint_ram2 IS

component wrapped_dint_ram2
	port (
	A: IN std_logic_VECTOR(4 downto 0);
	CLK: IN std_logic;
	D: IN std_logic_VECTOR(0 downto 0);
	WE: IN std_logic;
	DPRA: IN std_logic_VECTOR(4 downto 0);
	QDPO_CLK: IN std_logic;
	QDPO: OUT std_logic_VECTOR(0 downto 0);
	QSPO: OUT std_logic_VECTOR(0 downto 0);
	QDPO_RST: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_dint_ram2 use entity XilinxCoreLib.C_DIST_MEM_V6_0(behavioral)
		generic map(
			c_qualify_we => 0,
			c_mem_type => 2,
			c_has_qdpo_rst => 1,
			c_has_qspo => 1,
			c_has_qspo_rst => 0,
			c_has_dpo => 0,
			c_has_qdpo_clk => 1,
			c_has_d => 1,
			c_qce_joined => 0,
			c_width => 1,
			c_reg_a_d_inputs => 0,
			c_latency => 1,
			c_has_we => 1,
			c_has_spo => 0,
			c_depth => 32,
			c_has_i_ce => 0,
			c_default_data => "0",
			c_default_data_radix => 1,
			c_has_dpra => 1,
			c_has_clk => 1,
			c_enable_rlocs => 1,
			c_generate_mif => 1,
			c_has_qspo_ce => 0,
			c_addr_width => 5,
			c_has_qdpo_srst => 0,
			c_mux_type => 0,
			c_has_spra => 0,
			c_has_qdpo => 1,
			c_mem_init_file => "dint_ram2.mif",
			c_reg_dpra_input => 0,
			c_has_rd_en => 0,
			c_has_qspo_srst => 0,
			c_read_mif => 0,
			c_sync_enable => 0,
			c_has_qdpo_ce => 0);
BEGIN

U0 : wrapped_dint_ram2
		port map (
			A => A,
			CLK => CLK,
			D => D,
			WE => WE,
			DPRA => DPRA,
			QDPO_CLK => QDPO_CLK,
			QDPO => QDPO,
			QSPO => QSPO,
			QDPO_RST => QDPO_RST);
END dint_ram2_a;

-- synopsys translate_on