dint_ram2.vho

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component dint_ram2
	port (
	A: IN std_logic_VECTOR(4 downto 0);
	CLK: IN std_logic;
	D: IN std_logic_VECTOR(0 downto 0);
	WE: IN std_logic;
	DPRA: IN std_logic_VECTOR(4 downto 0);
	QDPO_CLK: IN std_logic;
	QDPO: OUT std_logic_VECTOR(0 downto 0);
	QSPO: OUT std_logic_VECTOR(0 downto 0);
	QDPO_RST: IN std_logic);
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of dint_ram2: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of dint_ram2: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : dint_ram2
		port map (
			A => A,
			CLK => CLK,
			D => D,
			WE => WE,
			DPRA => DPRA,
			QDPO_CLK => QDPO_CLK,
			QDPO => QDPO,
			QSPO => QSPO,
			QDPO_RST => QDPO_RST);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file dint_ram2.vhd when simulating
-- the core, dint_ram2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".