dint_ram2.sym

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

VERSION 5
BEGIN SYMBOL dint_ram2
SYMBOLTYPE BLOCK
TIMESTAMP 2005 10 4 12 9 36
SYMPIN 0 48 Input D(0:0)
SYMPIN 0 80 Input A(4:0)
SYMPIN 0 112 Input DPRA(4:0)
SYMPIN 0 240 Input WE
SYMPIN 0 272 Input CLK
SYMPIN 0 336 Input QDPO_CLK
SYMPIN 0 432 Input QDPO_RST
SYMPIN 480 80 Output QSPO(0:0)
SYMPIN 480 144 Output QDPO(0:0)
RECTANGLE N 32 0 448 544 
BEGIN DISPLAY 36 48 PIN D(0:0) ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 48 32 48 
END LINE
BEGIN DISPLAY 36 80 PIN A(4:0) ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 80 32 80 
END LINE
BEGIN DISPLAY 36 112 PIN DPRA(4:0) ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 112 32 112 
END LINE
BEGIN DISPLAY 36 240 PIN WE ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 240 32 240 
BEGIN DISPLAY 36 272 PIN CLK ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 272 32 272 
BEGIN DISPLAY 36 336 PIN QDPO_CLK ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 336 32 336 
BEGIN DISPLAY 36 432 PIN QDPO_RST ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 432 32 432 
BEGIN DISPLAY 444 80 PIN QSPO(0:0) ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 448 80 480 80 
END LINE
BEGIN DISPLAY 444 144 PIN QDPO(0:0) ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 448 144 480 144 
END LINE
END SYMBOL