fft_test.xco

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

# Xilinx CORE Generator 6.1.03i; Cores Update # 1.01
# Username = Administrator
# COREGenPath = D:\Xilinx\coregen
# ProjectPath = E:\wlan\ise_project\TX_processor_16QAM_newtest\TX_processor_16QAMpart2\TX_processor_v2.1\TX_processor_v1.1
# ExpandedProjectPath = E:\wlan\ise_project\TX_processor_16QAM_newtest\TX_processor_16QAMpart2\TX_processor_v2.1\TX_processor_v1.1
# OverwriteFiles = true
# Core name: fft_test
# 
# This core contains one or more blocks that are generated by synthesis.
# The contents of these blocks will not be included in the following report.
# Please run map and par to determine resources used by the whole core.
# 
# Number of Primitives in design: 7756
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 2516
# Number of LUTs used in design: 2407
# Number of REG used in design: 2527
# Number of SRL16s used in design: 109
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 7
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Fast_Fourier_Transform Spartan3 Xilinx,_Inc. 2.1
CSET rounding_modes = Convergent_Rounding
CSET ce = false
CSET scaling_options = Scaled
CSET memory_options_phase_factors = Block_RAM
CSET output_data_width = 16
CSET input_width = 16
CSET transform_length = 64
CSET create_rpm = false
CSET memory_options_data = Block_Ram
CSET implementation_options = Radix_4_Burst_IO
CSET component_name = fft_test
CSET phase_factor_width = 16
CSET sclr = true
GENERATE