channge20_new.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

module channge20(clk20M,clk60M,reset,inEn,outEn,dataInR,dataInI,dataOutR,dataOutI,bitIndexOut);
  input clk20M;
  input clk60M;
  input reset;
  input inEn;
  input [7:0]dataInR;
  input [7:0]dataInI; 
 
  output outEn;
  output [7:0]dataOutR;
  output [7:0]dataOutI;	
  output [5:0] bitIndexOut; 
  
  reg [5:0] bitIndexOut; 
  wire [7:0]dataOutR;
  wire [7:0]dataOutI;
  reg [7:0]dataInR_buf;
  reg [7:0]dataInI_buf;
 

  reg En;
  wire clk60M;



always @(posedge clk60M or negedge reset)
  begin
    if(!reset)
	  	begin
		  En<=0;
		  dataInR_buf<=0;
		  dataInI_buf<=0;
	
		end
	 else begin
	        if(inEn)
			    begin
				   dataInR_buf<=dataInR;
					dataInI_buf<=dataInI;
				
					En<=1;
				 end
			  else begin
			      dataInR_buf<=0;
					dataInI_buf<=0;
				
					En<=0;
					 end
			end
  end

reg mode;
reg [5:0] k;

always @(posedge clk60M or negedge reset)
  begin
    if(!reset)
	   begin
	     k<=0;
		end
	 else begin
	       if(En) 
			   begin
			     if(k==63)
				    k<=0;
				  else
				    k<=k+1;  	  
				end
			end
	end
reg [7:0] r;
reg modetemp;
reg [1:0] cont;
always @(posedge clk60M or negedge reset)
 begin
   if(!reset)
	  begin 
	    r<=0;
		 modetemp<=0;
	
	  end
	else begin
	       if(En)
			    begin
					if(r==63)
					  begin
					     modetemp<=1;
						  r<=0;
						 
					  end
					else 
					  begin
					     r<=r+1;
						  modetemp<=0;
					  end
				 end
			 else
			   begin
				 r<=0;
				 modetemp<=0;
				end
		  end
 end

always @(posedge clk60M or negedge reset)
 begin
   if(!reset)
	  begin 
		 cont<=2'b0;
		 mode<=0;
		end
   else
	  begin
		 if (cont==2'b11)
		    begin
			  mode<=0;
			  cont<=0;
			 end
		 else if (modetemp)
		    begin
			    mode<=1;
				 cont<=cont+1;
			 end
       else 
		    begin
			  if(mode)
		      cont<=cont+1; 
			  else
			    cont<=0;
			 end	       
	  end
 end

reg [5:0] t;
reg outEn;
reg flag;
always @(posedge clk20M or negedge reset)
  begin
    if(!reset)
		begin
	     t<=0;
		  outEn<=0;	
		  flag<=0;
		
		end
	 else begin
	        if(mode)
			    begin
				   flag<=1;
				 end
			  if(flag)
					begin
						outEn<=1;
					
	               if(t==63)
			             begin
							   t<=0;
								flag<=0;
							 end
			         else t<=t+1;
				   end
			   else outEn<=0;
			end
  end

always @(posedge clk20M or negedge reset)
  begin
    if(!reset)
		   bitIndexOut<=0;
		else
			bitIndexOut<=t;
  end

 dataromr dataromr (    //BRAM for real part: input 60MHz, output 20MHz, depth 64 bytes
    .addra(k),
    .addrb(t),
    .clka(clk60M),
    .clkb(clk20M),
    .dina(dataInR_buf),
    .doutb(dataOutR),
    .enb(flag),
    .wea(En));

 dataromi dataromi (    //BRAM for image part: input 60MHz, output 20MHz, depth 64 bytes
    .addra(k),
    .addrb(t),
    .clka(clk60M),
    .clkb(clk20M),
    .dina(dataInI_buf),
    .doutb(dataOutI),
    .enb(flag),
    .wea(En));
endmodule