fft_test.vhd

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

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-- You must compile the wrapper file fft_test.vhd when simulating
-- the core, fft_test. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY fft_test IS
	port (
	xn_re: IN std_logic_VECTOR(15 downto 0);
	xn_im: IN std_logic_VECTOR(15 downto 0);
	start: IN std_logic;
	unload: IN std_logic;
	nfft: IN std_logic_VECTOR(3 downto 0);
	nfft_we: IN std_logic;
	fwd_inv: IN std_logic;
	fwd_inv_we: IN std_logic;
	scale_sch: IN std_logic_VECTOR(5 downto 0);
	scale_sch_we: IN std_logic;
	sclr: IN std_logic;
	clk: IN std_logic;
	xk_re: OUT std_logic_VECTOR(15 downto 0);
	xk_im: OUT std_logic_VECTOR(15 downto 0);
	xn_index: OUT std_logic_VECTOR(5 downto 0);
	xk_index: OUT std_logic_VECTOR(5 downto 0);
	rfd: OUT std_logic;
	busy: OUT std_logic;
	dv: OUT std_logic;
	edone: OUT std_logic;
	done: OUT std_logic;
	ovflo: OUT std_logic);
END fft_test;

ARCHITECTURE fft_test_a OF fft_test IS

component wrapped_fft_test
	port (
	xn_re: IN std_logic_VECTOR(15 downto 0);
	xn_im: IN std_logic_VECTOR(15 downto 0);
	start: IN std_logic;
	unload: IN std_logic;
	nfft: IN std_logic_VECTOR(3 downto 0);
	nfft_we: IN std_logic;
	fwd_inv: IN std_logic;
	fwd_inv_we: IN std_logic;
	scale_sch: IN std_logic_VECTOR(5 downto 0);
	scale_sch_we: IN std_logic;
	sclr: IN std_logic;
	clk: IN std_logic;
	xk_re: OUT std_logic_VECTOR(15 downto 0);
	xk_im: OUT std_logic_VECTOR(15 downto 0);
	xn_index: OUT std_logic_VECTOR(5 downto 0);
	xk_index: OUT std_logic_VECTOR(5 downto 0);
	rfd: OUT std_logic;
	busy: OUT std_logic;
	dv: OUT std_logic;
	edone: OUT std_logic;
	done: OUT std_logic;
	ovflo: OUT std_logic);
end component;

-- Configuration specification 
	for all : wrapped_fft_test use entity XilinxCoreLib.xfft_v2_1(behavioral)
		generic map(
			c_has_ce => 0,
			c_has_bfp => 0,
			c_output_width => 16,
			c_input_width => 16,
			c_nfft_max => 6,
			c_has_scaling => 1,
			c_enable_rlocs => 0,
			c_has_ovflo => 0,
			c_has_rounding => 1,
			c_arch => 1,
			c_data_mem_type => 1,
			c_has_nfft => 1,
			c_has_bypass => 1,
			c_has_sclr => 1,
			c_twiddle_mem_type => 1,
			c_twiddle_width => 16);
BEGIN

U0 : wrapped_fft_test
		port map (
			xn_re => xn_re,
			xn_im => xn_im,
			start => start,
			unload => unload,
			nfft => nfft,
			nfft_we => nfft_we,
			fwd_inv => fwd_inv,
			fwd_inv_we => fwd_inv_we,
			scale_sch => scale_sch,
			scale_sch_we => scale_sch_we,
			sclr => sclr,
			clk => clk,
			xk_re => xk_re,
			xk_im => xk_im,
			xn_index => xn_index,
			xk_index => xk_index,
			rfd => rfd,
			busy => busy,
			dv => dv,
			edone => edone,
			done => done,
			ovflo => ovflo);
END fft_test_a;

-- synopsys translate_on