fft_test.vho

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component fft_test
	port (
	xn_re: IN std_logic_VECTOR(15 downto 0);
	xn_im: IN std_logic_VECTOR(15 downto 0);
	start: IN std_logic;
	unload: IN std_logic;
	nfft: IN std_logic_VECTOR(3 downto 0);
	nfft_we: IN std_logic;
	fwd_inv: IN std_logic;
	fwd_inv_we: IN std_logic;
	scale_sch: IN std_logic_VECTOR(5 downto 0);
	scale_sch_we: IN std_logic;
	sclr: IN std_logic;
	clk: IN std_logic;
	xk_re: OUT std_logic_VECTOR(15 downto 0);
	xk_im: OUT std_logic_VECTOR(15 downto 0);
	xn_index: OUT std_logic_VECTOR(5 downto 0);
	xk_index: OUT std_logic_VECTOR(5 downto 0);
	rfd: OUT std_logic;
	busy: OUT std_logic;
	dv: OUT std_logic;
	edone: OUT std_logic;
	done: OUT std_logic;
	ovflo: OUT std_logic);
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of fft_test: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fft_test: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : fft_test
		port map (
			xn_re => xn_re,
			xn_im => xn_im,
			start => start,
			unload => unload,
			nfft => nfft,
			nfft_we => nfft_we,
			fwd_inv => fwd_inv,
			fwd_inv_we => fwd_inv_we,
			scale_sch => scale_sch,
			scale_sch_we => scale_sch_we,
			sclr => sclr,
			clk => clk,
			xk_re => xk_re,
			xk_im => xk_im,
			xn_index => xn_index,
			xk_index => xk_index,
			rfd => rfd,
			busy => busy,
			dv => dv,
			edone => edone,
			done => done,
			ovflo => ovflo);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file fft_test.vhd when simulating
-- the core, fft_test. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".