fft_burst.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

module fft_Burst(bitInR,bitInI,inEn,FFT_set,Gclk,rst_n,dv,
              bitOutR,bitOutI,outEn);  

input [7:0] bitInR;
input [7:0] bitInI;
input inEn;
input FFT_set;
input Gclk;
input rst_n;

output [7:0] bitOutR;
output [7:0] bitOutI;
output outEn;
output dv;

reg start;                        //start ip core, enable for 1 cycle high. 4 cycles before input data
reg [3:0] nfft;					    //set number of FFT for ip core, 64->0110
reg nfft_we;						    //write nfft enable
reg fwd_inv;						    //chose FFT or IFFT for ip core, high level is FFT
reg fwd_inv_we;					    //write fwd_inv enable 
reg [5:0] scale_sch;    			 //scale for ip core, in case the overflow of data
reg scale_sch_we;					    //write scale_sch enable
reg rdy;							       //ready for input for ip core
reg nd;							       //enable input of ip core
reg [15:0] xn_re;					    //input real part register for ip core
reg [15:0] xn_im;					    //input image part register for ip core
reg [7:0] bitOutR;					 //output real part register
reg [7:0] bitOutI;					 //output image part register
reg outEn;						       //synchronize with output, as handshake with next module

wire [5:0] xn_index;				    //index of input for ip core
wire [5:0] xk_index;				    //index of output for ip core
wire rfd;							    //signal of ready for input data for ip core
wire busy;						       //output of ip core to indicate whether finish the process
wire dv;							       //output of ip core, enable output
wire edone;						       //output of ip core to indicate ready to output data, 1 cycle before done
wire done;						       //output of ip core to indicate ready to output data, 1 cycle before dataout
wire ovflo;						       //output of ip core to indicate the overflow of data
wire clr;

assign clr=~rst_n;                //reset of ip core, enable under high level


/***************************************************************************/
/******************** Set and control FFT  *********************************/
reg unload;
always @ (negedge rst_n or posedge Gclk)	
if (!rst_n)                                 //Initialize IP core                                             
  begin                              
  start<=1'b0;
  unload<=1'b0;
  nfft<=4'b0110;					    //number of FFT is 64
  nfft_we<=1'b0;
  fwd_inv<=1'b0;					    //use as IFFT
  fwd_inv_we<=1'b0;
  scale_sch<=6'b101110;				    
  scale_sch_we<=1'b0;
  rdy<=1'b0;
  nd<=1'b0;
  xn_re<=16'h0000;
  xn_im<=16'h0000;

  end

else
  begin
  if (FFT_set)                    //if FFT_set is high, enable all write control signals                  
    begin							    
    nfft_we<=1'b1;
    fwd_inv_we<=1'b1;
    scale_sch_we<=1'b1;	 
    end

  if (inEn)                       //if inEn is high, enable start and disable all write control signals
    begin                        		    		
    start<=1'b1;
    nfft_we<=1'b0;
    fwd_inv_we<=1'b0;
    scale_sch_we<=1'b0;
    end
  else
    start<=1'b0; 
    
  if (rfd)                                 
    begin                        		    				
    rdy<=rfd;
    nd<=rdy;
    end
  else 
    begin
	   rdy<=rfd;
		nd<=rdy;
	 end	  
  if (nd)							    //If new data is high, input data.
    begin                         //The input of IP core is 16 bit. notice the high bits which indicate sign of data 
	 xn_re[11]<=bitInR[7];
    xn_re[12]<=bitInR[7];
    xn_re[13]<=bitInR[7];
    xn_re[14]<=bitInR[7];
    xn_re[15]<=bitInR[7];
    xn_im[10:3]<=bitInI;			//we enlarge the input data by 8 times
    xn_im[11]<=bitInI[7];
    xn_im[12]<=bitInI[7];
    xn_im[13]<=bitInI[7];
    xn_im[14]<=bitInI[7];
    xn_im[15]<=bitInI[7];
    end

  else
    begin
    xn_re<=16'h0000;
    xn_im<=16'h0000;    
    end   
								    
  if (done)	
    begin	      			    
	  unload<=1'b1;
	 end
  else unload<=1'b0;	  							    
  end


/********************************************************************/
/********************  FFT ip core  *********************************/

fft_test fft(
    .xn_re(xn_re),
    .xn_im(xn_im),
    .start(start),
	 .unload(unload),
    .nfft(nfft),
    .nfft_we(nfft_we),
    .fwd_inv(fwd_inv),
    .fwd_inv_we(fwd_inv_we),
    .scale_sch(scale_sch),
    .scale_sch_we(scale_sch_we),
    .sclr(clr),
    .clk(Gclk),
    .xk_re(xk_re),
    .xk_im(xk_im),
    .xn_index(xn_index),
    .xk_index(xk_index),
    .rfd(rfd),
    .busy(busy),
    .dv(dv),
    .edone(edone),
    .done(done),
    .ovflo(ovflo));

/***************************************************************************/
/********************      IFFT output     *********************************/

always @ (negedge rst_n or posedge Gclk)	
if (!rst_n)                                                
  begin                              
  bitOutR<=16'h00;
  bitOutI<=16'h00;
  outEn<=1'b0;
  end

else
  begin							    
  if (dv)                         //If dv is enable, output data's lowest 8 bits.
    begin							
    bitOutR<=xk_re[7:0];
    bitOutI<=xk_im[7:0];
    outEn<=1'b1;   
    end
  else
    begin
    bitOutR<=8'h00;
    bitOutI<=8'h00;
    outEn<=1'b0;
    end

  end


endmodule