fft_test.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file fft_test.v when simulating
// the core, fft_test. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Guide".

module fft_test (
	xn_re,
	xn_im,
	start,
	unload,
	nfft,
	nfft_we,
	fwd_inv,
	fwd_inv_we,
	scale_sch,
	scale_sch_we,
	sclr,
	clk,
	xk_re,
	xk_im,
	xn_index,
	xk_index,
	rfd,
	busy,
	dv,
	edone,
	done,
	ovflo);    // synthesis black_box

input [15 : 0] xn_re;
input [15 : 0] xn_im;
input start;
input unload;
input [3 : 0] nfft;
input nfft_we;
input fwd_inv;
input fwd_inv_we;
input [5 : 0] scale_sch;
input scale_sch_we;
input sclr;
input clk;
output [15 : 0] xk_re;
output [15 : 0] xk_im;
output [5 : 0] xn_index;
output [5 : 0] xk_index;
output rfd;
output busy;
output dv;
output edone;
output done;
output ovflo;

// synopsys translate_off

	XFFT_V2_1 #(
		1,	// c_arch
		1,	// c_data_mem_type
		0,	// c_enable_rlocs
		0,	// c_has_bfp
		1,	// c_has_bypass
		0,	// c_has_ce
		1,	// c_has_nfft
		0,	// c_has_ovflo
		1,	// c_has_rounding
		1,	// c_has_scaling
		1,	// c_has_sclr
		16,	// c_input_width
		6,	// c_nfft_max
		16,	// c_output_width
		1,	// c_twiddle_mem_type
		16)	// c_twiddle_width
	inst (
		.XN_RE(xn_re),
		.XN_IM(xn_im),
		.START(start),
		.UNLOAD(unload),
		.NFFT(nfft),
		.NFFT_WE(nfft_we),
		.FWD_INV(fwd_inv),
		.FWD_INV_WE(fwd_inv_we),
		.SCALE_SCH(scale_sch),
		.SCALE_SCH_WE(scale_sch_we),
		.SCLR(sclr),
		.CLK(clk),
		.XK_RE(xk_re),
		.XK_IM(xk_im),
		.XN_INDEX(xn_index),
		.XK_INDEX(xk_index),
		.RFD(rfd),
		.BUSY(busy),
		.DV(dv),
		.EDONE(edone),
		.DONE(done),
		.OVFLO(ovflo),
		.CE(),
		.BLK_EXP());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of fft_test is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fft_test is "black_box"

endmodule