cp_adder.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

module CP_ADDER(CP_INR,CP_INI,CP_ND,CP_CLK,CP_RST,
                    CP_INDEX,CP_OUTR,CP_OUTI,CP_RDY);
    input [7:0] CP_INR;
    input [7:0] CP_INI;
    input CP_ND;
    input CP_CLK;
    input CP_RST;
    input [5:0] CP_INDEX;
    output [7:0] CP_OUTR;
    output [7:0] CP_OUTI;
    output CP_RDY;					

	 reg [7:0] CP_OUTR;
	 reg [7:0] CP_OUTI;
	 reg CP_RDY;

	 wire ND1;                // 第一个ram的写使能信号
	 wire ND2;                // 第二个ram的写使能信号
	 wire rst = ~CP_RST;      // ram的复位信号，低电平有效
	 wire [7:0] dout1R;       // ram输出缓存
	 wire [7:0] dout1I;
	 wire [7:0]	dout2R;
	 wire [7:0] dout2I;
	 reg i;
	 reg rdy;
	 reg [7:0] FIRSTR1;       // 用于存储第一个值
	 reg [7:0] FIRSTI1;
	 reg [7:0] FIRSTR2;
	 reg [7:0] FIRSTI2;
	 reg [5:0] q;
	 reg [5:0] j;

	 assign ND1 = CP_ND&(~i);
	 assign ND2 = CP_ND&i; 

	 bram1r bram1r(
	        .addra(CP_INDEX),
			  .dina(CP_INR),
			  .wea(ND1),
			  .clka(CP_CLK),
			  .addrb(q),
			  .enb(rdy),
			  .sinitb(rst),
			  .clkb(CP_CLK),
			  .doutb(dout1R));

	 bram1i bram1i(
	        .addra(CP_INDEX),
			  .dina(CP_INI),
			  .wea(ND1),
			  .clka(CP_CLK),
			  .addrb(q),
			  .enb(rdy),
			  .sinitb(rst),
			  .clkb(CP_CLK),
			  .doutb(dout1I));	

	 bram2r bram2r(
	        .addra(CP_INDEX),
			  .dina(CP_INR),
			  .wea(ND2),
			  .clka(CP_CLK),
			  .addrb(q),
			  .enb(rdy),
			  .sinitb(rst),
			  .clkb(CP_CLK),
			  .doutb(dout2R));

	 bram2i bram2i(
	        .addra(CP_INDEX),
			  .dina(CP_INI),
			  .wea(ND2),
			  .clka(CP_CLK),
			  .addrb(q),
			  .enb(rdy),
			  .sinitb(rst),
			  .clkb(CP_CLK),
			  .doutb(dout2I));	

	always @ ( negedge CP_RST or posedge CP_CLK )			 //  决定使用哪组ram
	  begin
	    if ( !CP_RST )
		   begin
			  i <= 0 ;
			end
		 else
		   begin
			  if ( CP_INDEX == 63 )
			   begin
				 i <= ~ i;
				end
			  else
			   begin
			    i <= i;
				end
			end
	  end

	always @ ( negedge CP_RST or posedge CP_CLK )				// ram的读使能信号
	  begin
	    if ( !CP_RST )
			  rdy <= 0;
		 else
		   begin
           if ( CP_INDEX == 62 )
              rdy <= 1;
           if( j == 63 )
              rdy <= 0 ;	
			end
	  end

	always @ ( negedge CP_RST or posedge CP_CLK )			//	ram的读地址	  
	  begin
	    if ( !CP_RST )
			  q <= 0;
		 else
		   begin
           if ( CP_INDEX == 63 || rdy)
              q <= q + 1;
			  else  
			     q <= 0;
			 end
		end

	always @ ( negedge CP_RST or posedge CP_CLK )
	  begin
	    if ( !CP_RST )
			  j <= 0;
		 else
		   begin
           if ( rdy )
              j <= q ;
			  else
			     j <= 0;
			 end
		end

	always @ ( negedge CP_RST or posedge CP_CLK )		  // 将符号的第一个值存起来，用于加窗
	  begin
	    if ( !CP_RST )
		   begin
			  FIRSTR1 <= 0;
			  FIRSTI1 <= 0;
			  FIRSTR2 <= 0;
			  FIRSTI2 <= 0;
			end
		 else
		   if ( CP_INDEX == 0 )
			  begin
			    case(i)
				  1'b0:
				   begin
			        FIRSTR1 <= CP_INR;
				     FIRSTI1 <= CP_INI;
					end
				  1'b1:
				   begin
			        FIRSTR2 <= CP_INR;
				     FIRSTI2 <= CP_INI;
				   end
			     default:
				   begin
					  FIRSTR1 <= 0;
					  FIRSTI1 <= 0;	
					  FIRSTR2 <= 0;
					  FIRSTI2 <= 0;
					end
				 endcase	  		 
			  end
	  end				 

	always @ ( negedge CP_RST or posedge CP_CLK )		  //  输出
	  begin
	    if ( !CP_RST )
		   begin
			  CP_OUTR <= 0;
			  CP_OUTI <= 0;
			  CP_RDY <= 0;
			end
		 else
		  begin 
          if ( CP_INDEX == 48 )                            // 加窗处理
			    begin
				   CP_RDY <= 1;
				   if ( ~i )
					  begin
				       CP_OUTR <= ( CP_INR + FIRSTR2 ) >> 1;
						 CP_OUTI <= ( CP_INI + FIRSTI2 ) >> 1;
					  end
					else
					  begin
				       CP_OUTR <= ( CP_INR + FIRSTR1 ) >> 1;
						 CP_OUTI <= ( CP_INI + FIRSTI1 ) >> 1;
					  end	
				 end
		   if ( CP_INDEX > 48 )
			   begin 
				  CP_OUTR <= CP_INR ;
				  CP_OUTI <= CP_INI;
				  CP_RDY <= 1;
				end
			else
			 begin
			 if( rdy ) 
			   begin
				  CP_RDY <= 1;
              if ( i )
				    begin
				      CP_OUTR <= dout1R ;
				      CP_OUTI <= dout1I ;
					 end
				  else
				    begin
				      CP_OUTR <= dout2R ;
				      CP_OUTI <= dout2I ;
					 end	
				end
			 else if ( (~rdy) && (~CP_ND)  )
				begin
			     CP_OUTR <= 0;
			     CP_OUTI <= 0;
			     CP_RDY <= 0;				  
			   end
			 end
		  end
	  end			    			 				    

endmodule