conv_encoder.v

来自「基于Xilinx+FPGA的OFDM通信系统基带设计-程序」· Verilog 代码 · 共 39 行

module conv_encoder(clk,aclr,data_in,nd,data_out_v,rdy);

input aclr;
input clk;
input data_in;
input nd;
output [1:0] data_out_v;
output rdy;

reg [6:1] shift_reg;
reg [1:0] data_out_v;
reg rdy;

always @ ( negedge aclr or posedge clk )
  begin 
    if ( ! aclr )
	   begin
		  shift_reg <= 6'b000000;
		  data_out_v <= 0;
		  rdy <= 0 ;
		end

    else 
	   if ( nd )
		  begin
		    data_out_v[0] <= shift_reg[6] + shift_reg[5] + shift_reg[3] + shift_reg[2] + data_in;
			 data_out_v[1] <= shift_reg[6] + shift_reg[3] + shift_reg[2] + shift_reg[1] + data_in;
			 rdy<=1;
			 shift_reg <= { shift_reg [5:1], data_in };
		  end
		else
		  rdy <= 0;

  end



endmodule