second.rpt

多功能电子钟 报时 闹钟 设置时间

setmin   : INPUT;

-- Node name is 'daout0' 
-- Equation name is 'daout0', type is output 
daout0   =  da10~153;

-- Node name is 'daout1' 
-- Equation name is 'daout1', type is output 
daout1   =  da11~153;

-- Node name is 'daout2' 
-- Equation name is 'daout2', type is output 
daout2   =  da12~153;

-- Node name is 'daout3' 
-- Equation name is 'daout3', type is output 
daout3   =  da13~153;

-- Node name is 'daout4' 
-- Equation name is 'daout4', type is output 
daout4   =  da20~155;

-- Node name is 'daout5' 
-- Equation name is 'daout5', type is output 
daout5   =  da21~155;

-- Node name is 'daout6' 
-- Equation name is 'daout6', type is output 
daout6   =  da22~155;

-- Node name is 'daout7' 
-- Equation name is 'daout7', type is output 
daout7   =  da23~155;

-- Node name is ':83' = 'da10~153' 
-- Equation name is 'da10~153', location is LC8_F6, type is buried.
da10~153 = DFFE( _EQ001, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ001 = !da10~153 & !_LC7_F1;

-- Node name is ':82' = 'da11~153' 
-- Equation name is 'da11~153', location is LC6_F6, type is buried.
da11~153 = DFFE( _EQ002, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ002 = !da10~153 &  da11~153 & !da13~153
         #  da10~153 & !da11~153 & !da13~153;

-- Node name is ':81' = 'da12~153' 
-- Equation name is 'da12~153', location is LC3_F6, type is buried.
da12~153 = DFFE( _EQ003, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ003 = !da11~153 &  da12~153 & !da13~153
         # !da10~153 &  da12~153 & !da13~153
         #  da10~153 &  da11~153 & !da12~153 & !da13~153;

-- Node name is ':80' = 'da13~153' 
-- Equation name is 'da13~153', location is LC5_F6, type is buried.
da13~153 = DFFE( _EQ004, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ004 =  da10~153 &  da11~153 &  da12~153 & !da13~153
         # !da10~153 & !da11~153 & !da12~153 &  da13~153;

-- Node name is ':87' = 'da20~155' 
-- Equation name is 'da20~155', location is LC3_F1, type is buried.
da20~155 = DFFE( _EQ005, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ005 = !da20~155 & !_LC2_F1 &  _LC7_F1
         #  da20~155 & !_LC7_F1;

-- Node name is ':86' = 'da21~155' 
-- Equation name is 'da21~155', location is LC1_F1, type is buried.
da21~155 = DFFE( _EQ006, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ006 = !da20~155 &  da21~155 & !_LC2_F1
         #  da20~155 & !da21~155 & !_LC2_F1 &  _LC7_F1
         #  da21~155 & !_LC7_F1;

-- Node name is ':85' = 'da22~155' 
-- Equation name is 'da22~155', location is LC4_F1, type is buried.
da22~155 = DFFE( _EQ007, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ007 =  da22~155 & !_LC2_F1 & !_LC5_F1
         # !da22~155 & !_LC2_F1 &  _LC5_F1 &  _LC7_F1
         #  da22~155 & !_LC7_F1;

-- Node name is ':84' = 'da23~155' 
-- Equation name is 'da23~155', location is LC8_F1, type is buried.
da23~155 = DFFE( _EQ008, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ008 =  da23~155 & !_LC7_F1;

-- Node name is 'enmin' 
-- Equation name is 'enmin', type is output 
enmin    =  _LC6_F1;

-- Node name is '|LPM_ADD_SUB:134|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_F1', type is buried 
_LC5_F1  = LCELL( _EQ009);
  _EQ009 =  da20~155 &  da21~155;

-- Node name is ':4' 
-- Equation name is '_LC6_F1', type is buried 
_LC6_F1  = DFFE( _EQ010, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ010 =  setmin
         #  _LC2_F1 &  _LC7_F1
         #  _LC6_F1 & !_LC7_F1;

-- Node name is ':106' 
-- Equation name is '_LC7_F1', type is buried 
!_LC7_F1 = _LC7_F1~NOT;
_LC7_F1~NOT = LCELL( _EQ011);
  _EQ011 = !da12~153 & !da13~153
         # !da11~153 & !da13~153
         # !da10~153 & !da13~153
         #  da10~153 &  da11~153 &  da12~153
         # !da10~153 & !da11~153 & !da12~153;

-- Node name is ':135' 
-- Equation name is '_LC2_F1', type is buried 
!_LC2_F1 = _LC2_F1~NOT;
_LC2_F1~NOT = LCELL( _EQ012);
  _EQ012 =  da20~155 &  da21~155 &  da22~155 &  da23~155
         # !da22~155 & !da23~155
         # !da20~155 & !da21~155 & !da23~155;



Project Information                                c:\vhdl\digclock\second.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,737K