📄 deled.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 1/ 96( 1%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\vhdl\digclock\deled.rpt
deled
** EQUATIONS **
s0 : INPUT;
s1 : INPUT;
s2 : INPUT;
s3 : INPUT;
-- Node name is 'daout0'
-- Equation name is 'daout0', type is output
daout0 = _LC8_A10;
-- Node name is 'daout1'
-- Equation name is 'daout1', type is output
daout1 = _LC3_B8;
-- Node name is 'daout2'
-- Equation name is 'daout2', type is output
daout2 = _LC6_A10;
-- Node name is 'daout3'
-- Equation name is 'daout3', type is output
daout3 = _LC6_B8;
-- Node name is 'daout4'
-- Equation name is 'daout4', type is output
daout4 = _LC1_B8;
-- Node name is 'daout5'
-- Equation name is 'daout5', type is output
daout5 = _LC7_B8;
-- Node name is 'daout6'
-- Equation name is 'daout6', type is output
daout6 = _LC4_B8;
-- Node name is 'daout7'
-- Equation name is 'daout7', type is output
daout7 = _LC2_A10;
-- Node name is ':390'
-- Equation name is '_LC7_A10', type is buried
_LC7_A10 = LCELL( _EQ001);
_EQ001 = s0 & !s1 & !s2 & !s3;
-- Node name is ':402'
-- Equation name is '_LC4_A10', type is buried
!_LC4_A10 = _LC4_A10~NOT;
_LC4_A10~NOT = LCELL( _EQ002);
_EQ002 = s2
# s1
# s0
# s3;
-- Node name is ':405'
-- Equation name is '_LC2_A10', type is buried
_LC2_A10 = LCELL( _EQ003);
_EQ003 = _LC4_A10
# _LC5_A10;
-- Node name is ':407'
-- Equation name is '_LC5_A10', type is buried
_LC5_A10 = LCELL( _EQ004);
_EQ004 = s1
# s3
# s0 & s2
# !s0 & !s2;
-- Node name is ':438'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ005);
_EQ005 = s3
# !s0 & !s1
# s0 & s1
# s1 & !s2
# !s0 & !s2;
-- Node name is '~462~1'
-- Equation name is '~462~1', location is LC1_A10, type is buried.
-- synthesized logic cell
!_LC1_A10 = _LC1_A10~NOT;
_LC1_A10~NOT = LCELL( _EQ006);
_EQ006 = s0 & s1
# !s2 & !s3
# !s0 & !s1 & !s3
# s2 & s3
# !s0 & !s1 & s2
# s1 & s3
# s1 & !s2;
-- Node name is ':471'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = LCELL( _EQ007);
_EQ007 = !s0 & !s1 & !s3
# !s1 & s2 & !s3
# !s0 & s2 & !s3
# !s1 & !s2 & s3
# !s0 & !s1 & !s2
# s0 & s1 & !s3;
-- Node name is ':504'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ008);
_EQ008 = s1 & !s2 & !s3
# !s0 & !s2 & !s3
# s0 & !s1 & s2 & !s3
# !s0 & s1 & !s3
# !s1 & !s2 & s3
# !s0 & !s1 & !s2;
-- Node name is ':537'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = LCELL( _EQ009);
_EQ009 = !s0 & !s2
# !s0 & s1
# s2 & s3
# s1 & s3
# !s0 & s3
# !s1 & !s2 & !s3;
-- Node name is ':569'
-- Equation name is '_LC3_A10', type is buried
_LC3_A10 = LCELL( _EQ010);
_EQ010 = s3
# !s1
# !s0 & s2;
-- Node name is ':570'
-- Equation name is '_LC6_A10', type is buried
_LC6_A10 = LCELL( _EQ011);
_EQ011 = _LC7_A10
# _LC4_A10
# _LC3_A10;
-- Node name is ':605'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = LCELL( _EQ012);
_EQ012 = s3
# !s1 & s2
# !s0 & s2
# !s0 & s1
# s1 & !s2;
-- Node name is ':638'
-- Equation name is '_LC8_A10', type is buried
_LC8_A10 = LCELL( _EQ013);
_EQ013 = !_LC1_A10 & _LC3_A10 & !_LC4_A10 & _LC5_A10;
Project Information c:\vhdl\digclock\deled.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,726K
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