changelog

eCos操作系统源码

	(1999-02-24  Hugo Tyson  <[e-mail]>)

	* tests/sparc_ex.c (sparc_ex_main): 
	For all traps except the USER_TRAP, install the default VSR
	hal_default_exception_vsr(); this is so that this test catches
	exception ie. is able to work, even when we are playing nice with
	CygMon and GDB.  The USER_TRAP is left so that breakpoints work,
	for the test infrastructure.

	(1999-02-22  Hugo Tyson  <[e-mail]>)

	* src/vectors.S (real_vector): Remove old testing code.  Add delay
	NOPs after writes to %wim and %psr for safety.  Leave installing
	the trap vector to platform-specific code, along with RAM control
	and cache initialization.

	* src/vec_ivsr.S (hal_default_interrupt_vsr): Add delay NOPs after
	writing the %wim before doing a restore; that was a bug that was.

	* src/vec_xvsr.S (hal_default_exception_vsr): same change.

	* src/hal_intr.c: Remove platform-specific clock period variable; it
	happens that both platforms sim and sleb have one, but it's not a
	requirement of the target architecture.

	* src/hal_boot.c (cyg_hal_start): Move diddling the sim-specific
	watchdog into platform-specific startup code viz. new routines
	hal_board_{pre/post}start().

	* src/context.S: a couple of extra NOPs to ensure that %wim and
	%psr changes work on real hardware.

	(1999-02-22  Hugo Tyson  <[e-mail]>)

	* include/hal_arch.h (HAL_SET_GDB_REGISTERS): 
	Remove warning about unused var 'cos of the incompleteness of
	these macros; gdb interworking is not yet supported.

1999-02-25  Nick Garnett  <[e-mail]>

	* include/vectors.h:
	Changed label used to access scheduler lock to one that is not
	mangled by C++. This is intended to make support for interrupt
	handling in non-kernel configurations easier.	

1999-02-20  Jonathan Larmour  <[e-mail]>

	* include/hal_arch.h: 
	Rename deliver_exception() -> cyg_hal_deliver_exception()
	QA improvements
	
	* include/hal_intr.h:
	Reorganise vector/interrupt/exception names according to purpose
	Rename exception_handler() -> cyg_hal_exception_handler()
	QA improvements

	* src/hal_intr.c:
	Rename exception_handler() -> cyg_hal_exception_handler()
	Rename deliver_exception() -> cyg_hal_deliver_exception()
	Rename CYG_ISR_COUNT -> CYGNUM_HAL_ISR_COUNT
	QA improvements

	* src/vec_ivsr.S:
	* src/vec_xvsr.S:
	Rename CYG_ISR_COUNT -> CYGNUM_HAL_ISR_COUNT
	QA improvements

	* tests/sparc_ex.c:
	Rename CYG_EXCEPTION_* -> CYGNUM_HAL_EXCEPTION_*
	Rename CYG_VECTOR_UNALIGNED -> CYGNUM_HAL_VECTOR_UNALIGNED

1999-02-12  Hugo Tyson  <[e-mail]>

	* src/context.S (hal_thread_load_context, hal_setjmp):
	Disable interrupts (but not traps) while doing the flush of all my
	callers and their callers' callers register sets to the stack.
	There is evidence that the inconsistency in the stack during this
	is a bad thing, though I have to admit that I don't see exactly
	how it goes wrong.  Partly, it's impossible to debug, so if the
	problem I saw (a SEGV in instrumentation of interrupt_end()) is
	reproduced with this change, I'll have more to go on.  This is a
	conservative change in that sense.
	
	* include/hal_arch.h (HAL_FLUSH_REGISTERS_TO_STACK): 
	Disable interrupts but not traps while doing this.  Ditto.

1999-02-12  Hugo Tyson  <[e-mail]>

	* include/pkgconf/hal_sparclite.h (CYGNUM_HAL_MINIMUM_STACK_SIZE):
	Define a minimal sensible stack size for apps to use.  Note that
	this file is included by hal_arch.h and so is available to all HAL
	users, and in fact almost everyone by default.

1999-02-12  Hugo Tyson  <[e-mail]>

	* src/hal_intr.c (exception_handler): 
	Include <cyg/infra/cyg_ass.h> so that the CYG_FAIL() in some
	configurations actually compiles (actually: links).
	combo{22,18,10,6} were thus afflicted.

1999-02-11  Hugo Tyson  <[e-mail]>

	* tests/sparc_ex.c (do_test): Make the test run for much less time
	when CYG_USE_TRACING and in any case bleat periodically about how
	successful it is to prevent testing system timeouts.  Also move
	the test routines (those which provoke the exception) to the end
	so that (ever helpful) -O3 cannot inline them and then "optimize"
	the result and thus spoil the whole damned test too.

1999-02-08  John Dallaway  <[e-mail]>

	* include/pkgconf/hal_sparclite.h: Correct capitalization of
	'SPARClite'.

1999-02-08  John Dallaway  <[e-mail]>

	* src/sparclite.ld: New MLT-compatible linker script
	* src/PKGconf.mak: Add build rules for sparclite.ld

1999-02-04  Hugo Tyson  <[e-mail]>

	* src/vec_ivsr.S (hal_default_interrupt_vsr): Preserve global
	registers over interrupts, and implement support for
	CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ie. save a
	minimal register set rather than a maximal.  Create a saved
	register set whose address is passed to the interrupt handler
	(though it may well be mostly empty).
	[also tidied up trailing tabs and long blank lines]

	* src/vec_xvsr.S (hal_default_exception_vsr): Preserve all
	registers over interrupts; create a saved register set whose
	address is passed to the exception handler so it can modify it.
	[also tidied up trailing tabs and long blank lines]

	* src/context.S( hal_setjmp, hal_longjmp):
	(hal_thread_switch_context,hal_thread_load_context): Implement
	CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM support; ie. save a minimal
	register set rather than a maximal.
	
	* include/hal_arch.h (HAL_FLUSH_REGISTERS_TO_STACK): New macro
	useful for writing exception handlers, for example.
	(HAL_GET_GDB_REGISTERS, HAL_SET_GDB_REGISTERS): provided initial
	dummy versions of these.

	* tests/sparc_ex.c: A test of the exception mechanism:
	deliberately cause unaligned accesses of various sizes and check
	we get exactly one trap and correctly step over it by modifying
	the saved register set whose address the exception ISR is handed.
	This test should be regarded as documentation for the exception
	handler API/ABI.
	
	* tests/PKGconf.mak (TESTS): Build sparc_ex.

1999-02-01  Hugo Tyson  <[e-mail]>

	* src/vectors.S (genuine_reset): 
	Include <cyg/hal/halboot.si> to set up RAM controllers, cache and
	the like - this is rather platform dependant.

1999-02-01  Hugo Tyson  <[e-mail]>

	* include/hal_intr.h (HAL_TRANSLATE_VECTOR): 
	Include a definition of this important macro.  Not.
	It's used when interrupt chaining is selected, BUT we the HAL make
	no distinction, it's up to the kernel to look after things.  So
	this macro is an assignment.

1999-01-28  Hugo Tyson  <[e-mail]>

	* include/hal_intr.h: 
	Get interrupt controller definitions from a board-specific file:
	#include <cyg/hal/hal_xpic.h>
	Get clock control definitions from a board-specific file:
	#include <cyg/hal/hal_clock.h>
	Delete the original definitions from this central file.
	
	* include/hal_cache.h: REMOVED to the simulator tree in the first
	instance; more generally to various board-specific files.


1999-01-26  Hugo Tyson  <[e-mail]>

	* include/hal_cache.h (HAL_DCACHE_ENABLE) (and its friends):
	Define initial empty placeholder versions of these so that cache
	tests build.  Well it's a start.
	
1999-01-21  Jonathan Larmour  <[e-mail]>

	* src/hal_boot.c (cyg_hal_invoke_constructors): 
	Add code to deal with CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
	Tidy up and update description header
	Shorten needlessly long lines
	Remove all traces of non-CYG_KERNEL_USE_INIT_PRIORITY code

1999-01-21  Hugo Tyson  <[e-mail]>

	* src/vectors.S (genuine_reset): Set the RAM size to 4MB in the
	erc32 simulator.

	* include/hal_io.h: New file; macros to access IO space, really a
	place holder at present.

	* include/hal_intr.h: Do not define WATCHDOG() macro.

	* src/hal_intr.c (hal_default_isr): Do not mess with the watchdog
	in the the default interrupt handler.

	* src/hal_boot.c (hal_zero_bss): use an efficient 8-byte zero.
	(hal_copy_data): use an efficient 8-byte copy.
	(cyg_hal_start): turn off the ERC32 watchdog timer before we start
	anything very time consuming.

	NB: the 8-byte copy changes require alignment in the linker
	script: see the Changelog in hal/sparclite/sim/... for details.

1999-01-19  Hugo Tyson  <[e-mail]>

	Modified files in arch:
	* include/hal_arch.h
	* include/hal_intr.h
	* src/PKGconf.mak
	* src/context.S
	* src/hal_intr.c
	* src/vec_ivsr.S
	* src/vec_xvsr.S
	* src/vectors.S

	New files in arch:
	* src/hal_boot.c	(bss initialization, constructors &c)
	* include/hal_cache.h	(empty but required header)

	Modified files in sim:
	* include/hal_diag.h

	Lots more progress; essentially, everything now works.

	Simulator's treatment of stdio is poor though, it doesn't work
	under pkgtest.  This has been slowing me up.

1999-01-14  Hugo Tyson  <[e-mail]>

	* ecc/ecc/hal/sparclite/...:

	Initial checkin of SPARClite HAL; it doesn't work yet, except the
	most trivial of tests - timer and interrupt manipulation stuff is
	entirely absent.

	Here's some documentation of the initial checkin tree; this will
	change, as platform dependent stuff moves correctly into the sim
	or <board> directories.

	arch/current/include:
		basetype.h	nothing much here.
		vectors.h	definitions of symbols shared between the
			various vector code assembler files, can be
			included in both C and assembler.
		hal_intr.h	various macros for clock and interrupt
			control plus the eCos vector numbering scheme; we
			map thus:
			what	SPARC trap type	    eCos vector numbers
			-----------------------------------------------
			(not used)   ---                0	
			interrupts (17-31)		1-15
			user traps (128-255)		16
			exceptions (1-9,36==4)		17-25
			others	   (10,?)		26
			-----------------------------------------------
			Trap types 5 and 6 which would be eCos vectors 21
			and 22 are handled in the trampoline code in
			file src/vectors.S
		hal_arch.h	definition of a thread context, plus
			macros for thread switching and the like.  Some
			ancillary bit twiddling macros and cache barriers
			too.

	arch/current/include/pkgconf:
		hal_sparclite.h 	pkgconf config/header file.
	
	arch/current/src:
		vectors.S	boot-up stuff, trampoline code that hangs
			on the interrupt/trap vector, handlers for window
			under/overflow.  Saves some state in registers
			then jumps to the interrupt or exception VSR
	   		respectively.
			Also instantiates the VSR table.
		vec_ivsr.S	the default interrupt VSR; it establishes
			a C calling environment (ie. anticipates a window
			overflow) then locks the scheduler, calls the ISR
			with appropriate arguments, and then interrupt_end()
			before undoing that environment, anticipating
			window underflow and returning to the interrupted
			instruction.
		vec_xvsr.S	the default exception AKA trap VSR; does
			the same as the interrupt one but without the
			scheduler lock or interrupt end.
		hal_intr.c	instantiates the ISR table used by the
			code above.
		context.S	context switch code, saves and loads up a
			whole register state, coroutine or longjump-like.
		icontext.c	initializes a context to "jump" to in
			context.S at the birth of a new thread.

	sim/current/include:
		hal_diag.h	macros to deal with debugging output via a
			fake serial device of some kind; initially empty,
			but definitely board/sim dependent.

	sim/current/include/pkgconf:
		hal_sparclite_sim.h 	pkgconf config/header file.

	sim/current/src:
		sim.ld		linker script bits for "sim" target.

//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================

//EOF ChangeLog