hal_arch.h

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#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ )             \
{                                                               \
    CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
    int _i_;                                                    \
                                                                \
    for( _i_ = 0; _i_ < 16; _i_++ )                             \
        _regval_[_i_] = (_regs_)->bank0[_i_];                   \
    for( _i_ = 0; _i_ < 16; _i_++ )                             \
        _regval_[16+_i_] = (_regs_)->bank1[_i_];                \
    _regval_[REG_VBR] = (_regs_)->vbr;                          \
    _regval_[REG_SSR_FIQ] = (_regs_)->ssr_fiq;                  \
    _regval_[REG_SSR_IRQ] = (_regs_)->ssr_irq;                  \
    _regval_[REG_SSR_SWI] = (_regs_)->ssr_swi;                  \
    _regval_[REG_SSR_EXPT] = (_regs_)->ssr_expt;                \
    _regval_[REG_SPC_FIQ] = (_regs_)->spc_fiq;                  \
    _regval_[REG_SPC_IRQ] = (_regs_)->spc_irq;                  \
    _regval_[REG_SPC_SWI] = (_regs_)->spc_swi;                  \
    _regval_[REG_SPC_EXPT] = (_regs_)->spc_expt;                \
    switch ((_regs_)->vector) {                                 \
      case CYGNUM_HAL_VECTOR_SWI:                               \
        _regval_[REG_SR] = (_regs_)->ssr_swi;                   \
        _regval_[REG_PC] = (_regs_)->spc_swi; break;            \
      case CYGNUM_HAL_VECTOR_IRQ:                               \
        _regval_[REG_SR] = (_regs_)->ssr_irq;                   \
        _regval_[REG_PC] = (_regs_)->spc_irq; break;            \
      case CYGNUM_HAL_VECTOR_FIQ:                               \
        _regval_[REG_SR] = (_regs_)->ssr_fiq;                   \
        _regval_[REG_PC] = (_regs_)->spc_fiq; break;            \
      default:                                                  \
        _regval_[REG_SR] = (_regs_)->ssr_expt;                  \
        _regval_[REG_PC] = (_regs_)->spc_expt; break;           \
    }                                                           \
                                                                \
}

// Copy a GDB ordered array into a HAL_SavedRegisters structure.
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ )             \
{                                                               \
    CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
    int _i_;                                                    \
                                                                \
    for( _i_ = 0; _i_ < 16; _i_++ )                             \
        (_regs_)->bank0[_i_] = _regval_[_i_];                   \
    for( _i_ = 0; _i_ < 16; _i_++ )                             \
        (_regs_)->bank1[_i_] = _regval_[16+_i_];                \
    (_regs_)->vbr = _regval_[REG_VBR];                          \
    (_regs_)->ssr_fiq = _regval_[REG_SSR_FIQ];                  \
    (_regs_)->ssr_irq = _regval_[REG_SSR_IRQ];                  \
    (_regs_)->ssr_swi = _regval_[REG_SSR_SWI];                  \
    (_regs_)->ssr_expt = _regval_[REG_SSR_EXPT];                \
    (_regs_)->spc_fiq = _regval_[REG_SPC_FIQ];                  \
    (_regs_)->spc_irq = _regval_[REG_SPC_IRQ];                  \
    (_regs_)->spc_swi = _regval_[REG_SPC_SWI];                  \
    (_regs_)->spc_expt = _regval_[REG_SPC_EXPT];                \
    switch (__get_trap_number()) {                              \
      case CYGNUM_HAL_VECTOR_SWI:                               \
        (_regs_)->ssr_swi = _regval_[REG_SR];                   \
        (_regs_)->spc_swi = _regval_[REG_PC]; break;            \
      case CYGNUM_HAL_VECTOR_IRQ:                               \
        (_regs_)->ssr_irq = _regval_[REG_SR];                   \
        (_regs_)->spc_irq = _regval_[REG_PC]; break;            \
      case CYGNUM_HAL_VECTOR_FIQ:                               \
        (_regs_)->ssr_fiq = _regval_[REG_SR];                   \
        (_regs_)->spc_fiq = _regval_[REG_PC]; break;            \
      default:                                                  \
        (_regs_)->ssr_expt = _regval_[REG_SR];                  \
        (_regs_)->spc_expt = _regval_[REG_PC]; break;           \
    }                                                           \
                                                                \
}

#define CYGARC_HAL_GET_PC_REG(_regs_, _val_)                    \
{                                                               \
    switch ((_regs_)->vector) {                                 \
      case CYGNUM_HAL_VECTOR_SWI:                               \
        (_val_) = (_regs_)->spc_swi; break;                     \
      case CYGNUM_HAL_VECTOR_IRQ:                               \
        (_val_) = (_regs_)->spc_irq; break;                     \
      case CYGNUM_HAL_VECTOR_FIQ:                               \
        (_val_) = (_regs_)->spc_fiq; break;                     \
      default:                                                  \
        (_val_) = (_regs_)->spc_expt; break;                    \
    }                                                           \
}

//--------------------------------------------------------------------------
// HAL setjmp
// Note: These definitions are repeated in context.S. If changes are
// required remember to update both sets.

#define CYGARC_JMP_BUF_R4        0
#define CYGARC_JMP_BUF_R5        2
#define CYGARC_JMP_BUF_R12       4
#define CYGARC_JMP_BUF_R13       8
#define CYGARC_JMP_BUF_R14      12
#define CYGARC_JMP_BUF_R15      16

#define CYGARC_JMP_BUF_SIZE     20

typedef cyg_uint16 hal_jmp_buf[CYGARC_JMP_BUF_SIZE/sizeof(cyg_uint16)];

externC int hal_setjmp(hal_jmp_buf env);
externC void hal_longjmp(hal_jmp_buf env, int val);

//-------------------------------------------------------------------------
// Idle thread code.
// This macro is called in the idle thread loop, and gives the HAL the
// chance to insert code. Typical idle thread behaviour might be to halt the
// processor.

externC void hal_idle_thread_action(cyg_uint32 loop_count);

#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)

//--------------------------------------------------------------------------
// Minimal and sensible stack sizes: the intention is that applications
// will use these to provide a stack size in the first instance prior to
// proper analysis.  Idle thread stack should be this big.

//    THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
//           THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!

// This is not a config option because it should not be adjusted except
// under "enough rope" sort of disclaimers.

// Typical case stack frame size: return link + 4 pushed registers + some locals.
#define CYGNUM_HAL_STACK_FRAME_SIZE (48)

// Stack needed for a context switch:
#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*CYG_HAL_MIPS_REG_SIZE)

// Interrupt + call to ISR, interrupt_end() and the DSR
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE) 

#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK

// An interrupt stack which is large enough for all possible interrupt
// conditions (and only used for that purpose) exists.  "User" stacks
// can be much smaller

#define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+      \
                                       CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+  \
                                       CYGNUM_HAL_STACK_FRAME_SIZE*8)
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024)

#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK 

// No separate interrupt stack exists.  Make sure all threads contain
// a stack sufficiently large.

#define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)

#endif

#endif /* __ASSEMBLER__ */


//--------------------------------------------------------------------------
// Macros for switching context between two eCos instances (jump from
// code in ROM to code in RAM or vice versa).
#define CYGARC_HAL_SAVE_GP()
#define CYGARC_HAL_RESTORE_GP()

//--------------------------------------------------------------------------
// Defines for status register bit access

#define CYGARC_SR_PM   (1<<31)
#define CYGARC_SR_RS1  (1<<30)
#define CYGARC_SR_RS0  (1<<29)
#define CYGARC_SR_BS   (1<<28)
#define CYGARC_SR_TE   (1<<26)
#define CYGARC_SR_FE   (1<<25)
#define CYGARC_SR_IE   (1<<24)



//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_HAL_ARCH_H
// End of hal_arch.h