vads.s

来自「eCos操作系统源码」· S 代码 · 共 1,394 行 · 第 1/4 页

write_loop:

   stb   r3,0(r0)         # Write 0xFF to address 0 - bits [24-31]
    
   bc    16,0,write_loop  # Decrement CTR, then branch if the decremented CTR
                          # is not equal to 0      

   #-------------------------------------------------------------------------
   # Program the PSDMR again turning off refresh services and changing the
   # SDRAM operation to "Mode Register Write". Then do a single write to an
   # arbitrary location. The various fields that will be programmed in the 
   # mode register on the SDRAM were specified in fields of the PSDMR, like
   # the BR (burst length) and the CL (CAS Latency) field.
   #-------------------------------------------------------------------------
   
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
   addis    r3,0,0x194E
   ori      r3,r3,0xB452
#else
   addis    r3,0,0x196E
   ori      r3,r3,0xB452
#endif
   stw      r3,CYGARC_REG_IMM_PSDMR(r4)

   addi     r3,0,0x00FF      # Load 0x000000FF into r3
   stb      r3,0(r0)         # Write 0xFF to address 0 - bits [24-31]
 
   #-------------------------------------------------------------------------
   # Program the PSDMR one last time turning on refresh services and changing 
   # the SDRAM operation to "Normal Operation". 
   #-------------------------------------------------------------------------
   
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
   addis    r3,0,0x414E
   ori      r3,r3,0xB452
#else
   addis    r3,0,0x416E
   ori      r3,r3,0xB452
#endif
   stw      r3,CYGARC_REG_IMM_PSDMR(r4)

   #----------------------------
   # return from init_60x_sdram
   #----------------------------
 
   bclr  20,0    # jump unconditionally to effective address in Link
                 # register


#########################################################################
# Function: init_local_sdram
#
# Description: This function programs the 4 Mbytes of SDRAM on the Local
#              Bus on the VADS board. This memory functions as storage for
#              connection tables and data buffers for the CPM peripherals.
#              Base and Option Register 4 are used. SDRAM Machine #2
#              and Chip Select #4 is used in the memory controller.
#
#  History:
#
#  Jan 9/99    jay      
#
#########################################################################        

init_local_sdram:

   ##################
   # Program Refresh
   ##################

   #-------------------------------------------------------------------------
   # Program the Local Bus Assigned SDRAM Refresh Timer (LSRT). Note that the
   # MPTPR register was programmed in the init_siu function which also
   # dictates the frequency to the LSRT block. Because the frequency rating
   # for the local bus SDRAM is same as the 60x SDRAM DIMM, only the LSRT
   # needs to be programmed and it is going to be the same as the PSRT
   # register.
   #-------------------------------------------------------------------------

   addi     r5,0,0x0010      # load 0x10 or 16 
   stb      r5,CYGARC_REG_IMM_LSRT(r4)      # store byte - bits[24-31]


   #########################
   # Program Bank Registers
   #########################


   #-------------------------------------------------------------------------
   # Base Register 4 (BR4): Bank 4 is assigned to the 4 Mbyte Local SDRAM 
   #                        bank that resides on the MPC8260 VADS board. The 
   #                        particulars are defined here. 
   #
   # - BA (Base Address) = 0x0400+0b for a total of 17 address bits. This 
   #                       value represents the upper 17 bits of the base 
   #                       address.
   #
   # - Bits 17-18 reserved. = 00 = cleared to 0.
   #
   # - PS (Port Size) = 11b = 32 bit port size
   #
   # - DECC (Data Error Correction and Checking) = 00 = Data errors checking
   #                                                    Disabled.
   #
   # - WP (Write Protect) = 0 = both read and write accesses are allowed
   #
   # - MS (Machine Select) = 011 = SDRAM Machine for Local bus Selected
   #
   # - EMEMC (External Memory Controller Enable) = 0 = 
   #
   #    Accesses are handled by the memory controller according to MSEL.
   #
   # - ATOM (Atomic Operation) = 00 = 
   #
   #    The address space controlled by the memory controller bank is not 
   #    used for atomic operations.
   #
   # - DR (Delayed Read) = 0 = Normal operation.
   #
   # - V (Valid Bit) =  1 = Valid bit set
   #-------------------------------------------------------------------------

   addis    r3,0,0x0400     # R3 holds the value temporarily
   ori      r3,r3,0x1861

   #-------------------------------------------------------------------------
   # Option Register 4 (OR4) for SDRAM Machine use: further SDRAM definitions
   #
   # - USDAM (Upper SDRAM Address Mask) = 11111b = 
   #
   #    We have masked all 5 bits which defines a maximum 128 Mbyte block Note
   #    that since the maximum SDRAM block size is 128 Mbyte, this field
   #    should always be 11111b.
   #
   # - SDAM (SDRAM Address Mask) = 1111100b = 4 Mbyte block.
   #
   # - LSDAM (Lower SDRAM Address Mask) = 00000b = Minimum of 1 Mbyte size.
   #
   # - BPD (Banks Per Device) = 00 = 2 internal banks per device.
   #
   # - ROWST (Row Start Address Bit) = 101 = A11 being the row start address
   #                                         bit.
   #
   # - Bit 22 Reserved - set to 0.
   #
   # - NUMR (Number of Row Address Lines) = 010 = 11 row address lines.
   #
   # - PMSEL (Page Mode Select) = 0 = back-to-back page mode (normal 
   #                                  operation).
   #
   # - IBID (Internal bank interleaving within same device disable) = 0 =
   # 
   #    Bank interleaving allowed.
   #
   # - AACKR (AACK/ release) = 0 = Normal operation.
   #
   # - Bits 29-31 Reserved - set to 0.
   #-------------------------------------------------------------------------

   addis    r5,0,0xFFC0     # R5 holds the value temporarily
   ori      r5,r5,0x1480

   #------------------
   # Write the values
   #------------------

   stw        r5,CYGARC_REG_IMM_OR4(r4)
   stw        r3,CYGARC_REG_IMM_BR4(r4)


   ###########################################
   # Perform Initialization sequence to SDRAM
   ###########################################

   #-------------------------------------------------------------------------
   # Program the Local SDRAM Mode Registr (LSDMR). This register is used
   # to configure operations pertaining to SDRAM on the Local bus. Turn off 
   # refresh services and change the SDRAM operation to "Precharge all banks".
   # Then do a single write to an arbitrary location. Writing 0 top
   # address 0 will do the trick.
   #
   # - Bit 0 is reserved. Set to 0.
   #
   # - RFEN (Refresh Enable) = 0 = Refresh services not required. This bit 
   #                               will be set later in this function as a 
   #                               last step.
   # 
   # - OP (SDRAM Operation) = 101 = Precharge all banks.
   #
   # - SDAM (Address Multiplex Size = 000 = 
   #
   #   Coming up the value for this field is one of the most confusing
   #   and non-intuitive steps in the SDRAM programming process. This is how
   #   it works... The SDRAM device is a 4 Mbit chip set that has a data  
   #   width of 32 bits or 4 bytes so the SDRAM will ignore the least 
   #   significant 2 bits. Given this information and knowing that the 
   #   number of row address lines is 11 and the column addresses is 8 and 
   #   also knowing that the row addresses must be multiplexed, write out the 
   #   following:
   #
   #   addresses ignored by SDRAM : A30 A31
   #
   #   column addresses: A22 A23 A24 A25 A26 A27 A28 A29
   #
   #   row addresses:   A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
   #
   #   When the memory controller multiplexes the addresses it puts the 
   #   column addresses out on the actual physical pins that matches its
   #   corresponding effective address bits.
   #
   #   According to the SDRAM Address Multiplexing table in the memory 
   #   controller section of the manual, SDAM selection of 000 fits the 
   #   address layout given above. Because the row is what is multiplexed 
   #   on designated column address pins, the row addresses are put out on the
   #   following column pins:
   #
   #.                                  8 column addresses
   #                                   |
   #   column ------------->A19 A20 A21|A22 A23 A24 A25 A26 A27 A28 A29
   #                         |   |   |   |   |   |   |   |   |   |   |
   #.  11 row addresses---->A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
   #   on corresponding
   #   column pins.
   #
   #   The row address is output on the address bus first, then the column 
   #   address.              
   #
   # - BSMA (Bank Select Multiplexed Address line) = 100 = A16-A18
   #
   #    For Local bus accesses, this field is a "do not care". BNKSEL[0:2]
   #    are associated with this field and these pins are only used for 
   #    60x compatible mode for 60x bus transactions.
   #
   # - SDA10 ("A10 Control") = 001 = A11 is the address pin used for the
   #                                 activate command.
   #
   # - RFRC (ReFresh ReCovery) = 101 = 
   #
   #   Once a refresh request is granted, the memory controller begins 
   #   issuing auto-refresh commands to each device associated with the 
   #   refresh timer in one clock intervals. After the last REFRESH 
   #   command is issued, the memory controller waits for 7 clocks before 
   #   the ACTIVATE command and before normal read/write operations can 
   #   resume.
   #
   # - PRETOACT (PREcharge TO ACTivate interval) = 010 = 
   #
   #   Wait 2 clock cycles before an activate command.
   #
   # - ACTTORW (ACTivate TO Read/Write interval) = 010 = 2 clock cycles.
   # 
   # - BL (Burst Length) = 1 = SDRAM burst length is 8. This is programmed 
   #                           into the SDRAM via the MRS commmand.
   #
   # - LDOTOPRE (Last Data Out TO PREcharge) = 00 = 
   #
   #   The delay required from the last data out to precharge state is 0 clock
   #   cycles.
   #                               
   # - WRC (Write Recovery Time) = 01 = 
   #
   #   Time needed to elapse before another operation is 1 clock cycle.
   #
   # - EAMUX (External Address MUltipleXing) = 0 No external address
   #                                             multiplexing.
   #
   # - BUFCMD (Buffer Control Lines) = 0 = Normal timing for the control
   #                                       lines.
   #
   # - CL (CAS Latency) = 10 = CAS latency is 2. Two cycles after column
   #                           address is registered, data is valid.
   #
   #-------------------------------------------------------------------------

   addis    r3,0,0x2886
   ori      r3,r3,0xA522
   stw      r3,CYGARC_REG_IMM_LSDMR(r4)

   addis    r2,0,0x0400
   addi     r3,0,-1
   stb      r3,0(r2)         # Write 0xFF to address 0x04000000
   

   #-------------------------------------------------------------------------
   # Program the LSDMR keeping refresh services off and changing the
   # SDRAM operation to "CBR Refresh". This step is responsible for issuing
   # a minimum of 8 auto-refresh commands. This is done by the SDRAM machine
   # by issuing the CBR Refresh command by programming the OP field of the 
   # PSDMR register and writing 0xFF 8 times to an arbitrary address.
   #-------------------------------------------------------------------------
   
   addis    r3,0,0x0886
   ori      r3,r3,0xA522
   stw      r3,CYGARC_REG_IMM_LSDMR(r4)

   #--------------------------------------------------
   # Loop 8 times, writing 0xFF to address 0x04000000
   #--------------------------------------------------

   addis r6,0,0
   ori   r6,r6,8
   mtspr CYGARC_REG_CTR,r6           # Load CTR with 8. 

   addi  r3,0,-1          # Load 0xFs into r3

write_loop1:

   stb   r3,0(r2)         # Write 0 to address 0x04000000
    
   bc    16,0,write_loop1 # Decrement CTR, then branch if the decremented CTR
                          # is not equal to 0      

   #-------------------------------------------------------------------------
   # Program the LSDMR again turning off refresh services and changing the
   # SDRAM operation to "Mode Register Write". Then do a single write to an
   # arbitrary location. The various fields that will be programmed in the 
   # mode register on the SDRAM were specified in fields of the LSDMR, like
   # the BR (burst length) and the CL (CAS Latency) field.
   #-------------------------------------------------------------------------
   
   addis    r3,0,0x1886
   ori      r3,r3,0xA522
   stw      r3,CYGARC_REG_IMM_LSDMR(r4)

   addi     r3,0,-1           
   stb      r3,0(r2)         # Write 0xFF to address 0x04000000
  
   #-------------------------------------------------------------------------
   # Program the LSDMR one last time turning on refresh services and changing 
   # the SDRAM operation to "Normal Operation". 
   #-------------------------------------------------------------------------
   
   addis    r3,0,0x4086
   ori      r3,r3,0xA522
   stw      r3,CYGARC_REG_IMM_LSDMR(r4)

   #------------------------------
   # return from init_local_sdram
   #------------------------------

   bclr  20,0    # jump unconditionally to effective address in Link
                 # register
                
#------------------------------------------------------------------------------
# end of vads.S